WM8802SCFV datasheet(14/65 Pages) WOLFSON

14 / 65 page

WM8802

Product Preview

PP Rev 1.1 April 2004

DEMODULATION FUNCTION WITHOUT USING PLL (TMCK)

The WM8802 has a function to process input bi-phase data using an external clock (external

synchronization function). In normal demodulation processing, the clock is generated in

synchronization with data by the built-in PLL; the data processing is performed using this clock. It is

possible to perform data processing by supplying a data synchronized clock instead of the clock

generated by the PLL via an independent transmission path.

The demodulation function can be used to set external synchronization function without using the

PLL by EXSYNC. PLLSEL should be set to 256fs and PRSEL0 should be set to 1 (setting frequency

to 1/1). The 256fs clock should then be synchronized with the input data to TMCK. As a result of

these settings, the same operation occurs as PLL demodulation processing with a 256fs clock. LPF

should remain unconnected as no loop filter is required.

The external synchronization function settings should be completed prior to bi-phase data input

(paying attention to the bandwidth of clock transmission path).

A high-precision clock system using an external PLL can also be configured by using the external

synchronization function.

OSCILLATION AMPLIFIERS (XIN, XOUT, MCK)

The WM8802 features a built-in oscillation amplifier. An oscillation circuit can be configured by

connecting a crystal resonator, feedback resistor and load capacitance across XIN and XOUT. When

connecting a crystal resonator, use a fundamental crystal resonator. Note that the load capacitance

depends on the crystal resonator characteristics.

The output of an external clock supply source should be connected to XIN if the built-in oscillation

amplifier is not used as the clock source. In this configuration it is not necessary to connect a

feedback resistor between XIN and XOUT.

A 12.288MHz or 24.576MHz clock can be supplied to XIN by setting XINSEL. If input frequency to

XIN changes it is necessary to set FSERR to 1, so that when the input data sampling frequency

changes, the result is not reflected in the error flag. Since the input frequency is then different to the

recommended frequency operation, the encoding result cannot be used for input fs calculations. In

this case, the input fs can be calculated by performing decimal division of the count value (FSDAT)

with 1/2000th of the XIN input frequency. For details, see Micro-controller Interface section.

Since the XIN clock serves as the reference for internal processing, the XINSEL setting should be

completed prior to bi-phase data input.

A clock should be supplied to XIN at the following times:

(1)

Detection of bi-phase data input

(2)

Clock source during PLL unlock

(3)

Input data sampling frequency calculation

(4)

Time definition during input data switching

(5)

External supply clock source (AD converter clock, etc.)

The oscillation amplifier automatically stops when the PLL is locked. However, it can also be set for

continuous operation with AMPOPR set to 1. Setting the continuous operation mode enables input

data detection and input sampling frequency calculation even when the PLL is locked; this has an

effect on the sound quality because the oscillation amplifier and PLL clock coexist.

RERR outputs an error (High) once the PLL is locked if the oscillation amplifier is set to continuous

operation by setting AMPOPR to 1. This occurs because, at the same time that the oscillation

amplifier goes into the operating state, the fs calculation value that is held when operation is stopped,

is reset. This error has no influence on the clock output, but RDATA is muted while this error occurs.

Therefore, the AMPOPR[0:1] setting must be completed either prior to bi-phase data input or during

PLL unlock.

WM8802SCFV 数据表(PDF) 14 Page - Wolfson Microelectronics plc

WM8802SCFV 数据表(HTML) 14 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

数据表下载