WM8802SCFV datasheet(44/65 Pages) WOLFSON

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WM8802

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PP Rev 1.1 April 2004

R system output clock setting:

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

CAU

CAL

DI15

DI14

DI13

DI12

DI11

DI10

DI9

DI8

CCB address: 0xE8;

Command address: 3

XRLRCK1

XRLRCK0

XRBCK1

XRBCK0

XRSEL1

XRSEL0

PRSEL1

PRSEL0

PRSEL [1:0]

RMCK output frequency setting during PLL lock

00: 1/2 of PLLSEL setting frequency (initial value)

01: 1/1 of PLLSEL setting frequency

10: 1/4 of PLLSEL setting frequency

11: Muted

XRSEL [1:0]

RMCK output frequency setting during XIN source

00: 1/1 of XINSEL setting frequency (initial value)

01: 1/2 of XINSEL setting frequency

10: 1/4 of XINSEL setting frequency

11: Muted

XRBCK [1:0]

RBCK output frequency setting during XIN source

00: 3.072MHz output (initial value)

01: 6.144MHz output

10: 12.288MHz output

11: Muted

XRLRCK [1:0]

RLRCK output frequency setting during XIN source

00: 48kHz output (initial value)

01: 96kHz output

10: 192kHz output

11: Muted

3.072MHz is output from RBCK if the RMCK frequency is set lower than RBCK when the XIN source

is used.

WM8802SCFV 数据表(PDF) 44 Page - Wolfson Microelectronics plc

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WM8802SCFV 数据表(PDF) 44 Page - Wolfson Microelectronics plc

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