WM8802SCFV datasheet(26/65 Pages) WOLFSON

26 / 65 page

WM8802

Product Preview

PP Rev 1.1 April 2004

OUTPUT DATA SWITCHING (SDIN, RDATA)

RDATA demodulation data is output when the PLL is locked and the SDIN input is selected This

switching is automatically performed according to the locked/unlocked status of the PLL. For details,

see the timing charts below.

Switch to a clock source synchronized to the SDIN data when SDIN input data is selected.

The SDIN input data can be output to RDATA regardless of the locked/unlocked status of the PLL

using RDTSTA setting.

The RDATA output data can be forcibly muted using the RDTMUT setting.

The PLL continues operating when the clock source is set to XIN using OCKSEL and RCKSEL as

long as its operation is not stopped using PLLOPR. The PLL status is continuously output from

RERR as long as error output is not forcibly set with RESTA. The processed information can also be

read with the micro-controller interface regardless of the PLL status.

RERR

(a) Lock-in stage

RDATA

UNLOCK

LOCK

(b) Unlock stage

RERR

RDATA

PLL locked status

LOCK

UNLOCK

SDIN data

Muted

Demodulation data

SDIN data

Demodulation data

Muted

PLL locked status

CKST

Figure 18 RDATA Output Data Switch Timing Chart

DATA BLOCK DIAGRAM (RX0 TO RX6, TX0, RXOUT, TDATA, RDATA, SDIN)

The RDATA output data is switched to SDIN input data using RDTSEL.

The SDIN input data can be input to the modulation function using TDTSEL.

The modulation output is an input to the Input Switch Multiplexer and can be output from RXOUT. It

is possible to use a signal that has been digitized with an A/D converter for digital recording output,

etc. using this function.

WM8802SCFV 数据表(PDF) 26 Page - Wolfson Microelectronics plc

WM8802SCFV 数据表(HTML) 26 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

数据表下载