WM8802SCFV datasheet(21/65 Pages) WOLFSON

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WM8802

PP Rev 1.1 April 2004

BI-PHASE SIGNAL INPUT / OUTPUT

BI-PHASE SIGNAL INPUT RECEPTION RANGE

The input data reception range depends on the PLL lock frequency setting set by PLLSEL. The

relationship between this setting and the guaranteed reception range is shown below.

PLL OUTPUT CLOCK SETTING

INPUT DATA RECEPTION RANGE

512fs (PLLSEL = 0)

28kHz to 105kHz

256fs (PLLSEL = 1)

28kHz to 195kHz

Table 10 Relationship Between PLL Output Clock Setting and Reception Range

(FSLIM[0:1] = 0)

The fs reception range for input data within the above PLL output clock setting range can be

controlled. This setting is performed using FSLIM[0:1]. When this function is used, input data that

exceeds the setting range is considered as an error and the clock source is automatically switched to

the XIN source. The RDATA output data then depends on the RDTSEL setting.

BI-PHASE SIGNAL INPUT/OUTPUT PINS (RX0 TO RX6, RXOUT)

There are 7 digital data input pins. Data modulated with the modulation function can also be

selected, therefore selection from a total of 8 signals is possible. However, the pins that can be

selected are restricted by the following conditions:

The six pins RX0 and RX2 to RX6 are TTL level input pins with 5V input level tolerable.

RX1 is a coaxial-compatible input pin with built-in amplifier that can receive up to 200mVp-p

data.

The demodulation input and RXOUT output signals can also be selected independently.

The demodulation data is selected with RISEL[0:2].

The RXOUT output data is selected with ROSEL[0:2].

RXOUT can be muted with RXOFF. Muting is recommended when not using RXOUT in order to

reduce clock jitter.

The data input status can be monitored with the RXMON setting. The status of each data input pin is

stored in CCB address 0xEA and output registers DO0 to DO7. Since this function uses the XIN

clock, the oscillation amplifier must be set to the continuous operation mode when RXMON is set.

Demodulation input pin switching can be performed during PLL unlock using the ULSEL setting. As a

result, data switching can be accurately communicated to peripheral devices.

The interval from pin switching through RISEL[0:2] until data is received is about 250

µs to 350µs.

This function also requires that the oscillation amplifier is set to the continuous operation mode.

Input pin selection

Internal supply signal

RX0

RX2

RX3

RX1

RX0

RX2

RX3

RX1

250

µµµµs to 350µµµµs

Figure 9 Input Pin Selection Processing via PLL Unlock

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