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LSM6DSR 数据表(PDF) 114 Page - STMicroelectronics |
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LSM6DSR 数据表(HTML) 114 Page - STMicroelectronics |
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114 / 168 page ![]() 11.38 EMB_FUNC_ODR_CFG_B (5Fh) Finite State Machine output data rate configuration register (r/w) Table 254. EMB_FUNC_ODR_CFG_B register 0(1) 1(2) 0(1) FSM_ODR1 FSM_ODR0 0(1) 1(2) 1(2) 1. This bit must be set to '0' for the correct operation of the device. 2. This bit must be set to '1' for the correct operation of the device Table 255. EMB_FUNC_ODR_CFG_B register description FSM_ODR[1:0] Finite State Machine ODR configuration: (00: 12.5 Hz; 01: 26 Hz (default); 10: 52 Hz; 11: 104 Hz) LSM6DSR EMB_FUNC_ODR_CFG_B (5Fh) DS11976 - Rev 2 page 114/168 |
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