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XIO2000AI 数据表(PDF) 31 Page - Texas Instruments |
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XIO2000AI 数据表(HTML) 31 Page - Texas Instruments |
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31 / 165 page  Introduction 22 April 2007 Revised October 2008 SCPS155C Table 2−12. Miscellaneous Terminals SIGNAL GZZ/ ZZZ BALL ZHC BALL ZHH BALL I/O TYPE CELL TYPE CLAMP RAIL EXTERNAL PARTS DESCRIPTION CLKRUN_EN B15 B13 B13 I LV CMOS VDD_33 Optional pullup resistor Clock run enable 0 = Clock run support disabled 1 = Clock run support enabled Note: The CLKRUN_EN input buffer has an internal active pulldown. EXT_ARB_EN A15 C12 B12 I LV CMOS VDD_33 Optional pullup resistor External arbiter enable 0 = Internal arbiter enabled 1 = External arbiter enabled Note: The EXT_ARB_EN input buffer has an internal active pulldown. GPIO0 // CLKRUN T05 M04 P03 I/O LV CMOS VDD_33 Optional pullup resistor General-purpose I/O 0/clock run. This terminal functions as a GPIO controlled by bit 0 (GPIO0_DIR) in the GPIO control register (see Section 4.59) or the clock run terminal. This terminal is used as clock run input when the bridge is placed in clock run mode. Note: In clock run mode, an external pullup resistor is required to prevent the CLKRUN signal from floating. Note: This terminal has an internal active pullup resistor. GPIO1 // PWR_OVRD U05 P03 P04 I/O LV CMOS VDD_33 − General-purpose I/O 1/power override. This terminal functions as a GPIO controlled by bit 1 (GPIO1_DIR) in the GPIO control register (see Section 4.59) or the power override output terminal. GPIO1 becomes PWR_OVRD when bits 22:20 (POWER_OVRD) in the general control register are set to 001b or 011b (see Section 4.65). Note: This terminal has an internal active pullup resistor. GPIO2 T06 M05 N04 I/O LV CMOS VDD_33 − General-purpose I/O 2. This terminal functions as a GPIO controlled by bit 2 (GPIO2_DIR) in the GPIO control register (see Section 4.59). Note: When PERST is deasserted, this terminal must be a 1b to enable the PCI Express 1.0a compatibility mode. Note: This terminal has an internal active pullup resistor. GPIO3 U06 N04 M04 I/O LV CMOS VDD_33 − General-purpose I/O 3. This terminal functions as a GPIO controlled by bit 3 (GPIO3_DIR) in the GPIO control register (see Section 4.59). Note: This terminal has an internal active pullup resistor. GPIO4 // SCL R07 P04 P05 I/O LV CMOS VDD_33 Optional pullup resistor GPIO4 or serial-bus clock. This terminal functions as serial-bus clock if a pullup resistor is detected on SDA. If a pulldown resistor is detected on SDA, this terminal functions as GPIO4. Note: In serial-bus mode, an external pullup resistor is required to prevent the SCL signal from floating. Note: This terminal has an internal active pullup resistor. |
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