XIO2000AI datasheet(79/165 Pages) TI

79 / 165 page

Classic PCI Configuration Space

April 2007 Revised October 2008

SCPS155C

4.47 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This

PCI register offset:

91h

Read-only

Default value:

00h

BIT NUMBER

RESET STATE

4.48 PCI Express Capabilities Register

This read-only register indicates the capabilities of the bridge related to PCI Express. See Table 4−24 for a

complete description of the register contents.

PCI register offset:

92h

Read-only

Default value:

0071h

BIT NUMBER

RESET STATE

Table 4−24. PCI Express Capabilities Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:14

RSVD

Reserved. Returns 00b when read.

13:9

INT_NUM

Interrupt message number. This field is used for MSI support and is implemented as read-only

00000b in the bridge.

SLOT

Slot implemented. This bit is not valid for the bridge and is read-only 0b.

7:4

DEV_TYPE

Device/port type. This read-only field returns 7h indicating that the device is a PCI Express-to-PCI

bridge.

3:0

VERSION

Capability version. This field returns 1h indicating revision 1 of the PCI Express capability.

XIO2000AI 数据表(PDF) 79 Page - Texas Instruments

XIO2000AI 数据表(HTML) 79 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载