XIO2000AI datasheet(73/165 Pages) TI

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Classic PCI Configuration Space

April 2007 Revised October 2008

SCPS155C

4.32 Power Management Capabilities Register

This read-only register indicates the capabilities of the bridge related to PCI power management. See

Table 4−18 for a complete description of the register contents.

PCI register offset:

52h

Read-only

Default value:

0602h

BIT NUMBER

RESET STATE

Table 4−18. Power Management Capabilities Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:11

PME_SUPPORT

PME support. This 5-bit field indicates the power states from which the bridge may assert PME.

Because the bridge never generates a PME except on a behalf of a secondary device, this field

is read-only and returns 00000b.

D2_SUPPORT

This bit returns a 1b when read, indicating that the function supports the D2 device power state.

D1_SUPPORT

This bit returns a 1b when read, indicating that the function supports the D1 device power state.

8:6

AUX_CURRENT

3.3 VAUX auxiliary current requirements. This field returns 000b since the bridge does not

generate PME from D3cold.

DSI

Device specific initialization. This bit returns 0b when read, indicating that the bridge does not

require special initialization beyond the standard PCI configuration header before a generic class

driver is able to use it.

RSVD

Reserved. Returns 0b when read.

PME_CLK

PME clock. This bit returns 0b indicating that the PCI clock is not needed to generate PME.

2:0

PM_VERSION

Power management version. If bit 26 (PCI_PM_VERSION_CTRL) in the general control register

(offset D4h, see Section 4.65) is 0b, then this field returns 010b indicating revision 1.1

compatibility. If PCI_PM_VERSION_CTRL is 1b, then this field returns 011b indicating revision

1.2 compatibility.

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