XIO2000AI datasheet(70/165 Pages) TI

70 / 165 page

Classic PCI Configuration Space

April 2007 Revised October 2008

SCPS155C

4.27 Interrupt Line Register

This read/write register is programmed by the system and indicates to the software which interrupt line the

bridge has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not yet

been assigned to the function. Since the bridge does not generate interrupts internally, this register is a scratch

pad register.

PCI register offset:

3Ch

Read/Write

Default value:

FFh

BIT NUMBER

RESET STATE

4.28 Interrupt Pin Register

The interrupt pin register is read-only 00h indicating that the bridge does not generate internal interrupts. While

the bridge does not generate internal interrupts, it does forward interrupts from the secondary interface to the

primary interface.

PCI register offset:

3Dh

Read-only

Default value:

00h

BIT NUMBER

RESET STATE

4.29 Bridge Control Register

The bridge control register provides extensions to the command register that are specific to a bridge. See

Table 4−17 for a complete description of the register contents.

PCI register offset:

3Eh

Read-only, Read/Write, Read/Clear

Default value:

0000h

BIT NUMBER

RESET STATE

Table 4−17. Bridge Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:12

RSVD

Reserved. Returns 0h when read.

DTSERR

Discard timer SERR enable. Applies only in conventional PCI mode. This bit enables the bridge to

generate either an ERR_NONFATAL (by default) or ERR_FATAL transaction on the primary

interface when the secondary discard timer expires and a delayed transaction is discarded from a

queue in the bridge. The severity is selectable only if advanced error reporting is supported.

0 = Do not generate ERR_NONFATAL or ERR_FATAL on the primary interface as a result of

the expiration of the secondary discard timer. Note that an error message can still be sent if

advanced error reporting is supported and bit 10 (DISCARD_TIMER_MASK) in the

secondary uncorrectable error mask register (offset 130h, see Section 5.11) is clear

(default).

1 = Generate ERR_NONFATAL or ERR_FATAL on the primary interface if the secondary

discard timer expires and a delayed transaction is discarded from a queue in the bridge

DTSTATUS

RCU

Discard timer status. This bit indicates if a discard timer expires and a delayed transaction is

discarded.

0 = No discard timer error

1 = Discard timer error

XIO2000AI 数据表(PDF) 70 Page - Texas Instruments

XIO2000AI 数据表(HTML) 70 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

XIO2000AI 数据表(PDF) 70 Page - Texas Instruments

XIO2000AI 数据表(HTML) 70 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载