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XIO2000AI 数据表(PDF) 40 Page - Texas Instruments

部件名 XIO2000AI
功能描述  XIO2000A/XIO2000AI PCI Express to PCI Bus Translation Bridge
PDF  165 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

XIO2000AI 数据表(HTML) 40 Page - Texas Instruments

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Feature/Protocol Descriptions
31
April 2007 Revised October 2008
SCPS155C
3.4.5 MSI Messages Generated from the Serial IRQ Interface
When properly configured, the bridge converts PCI bus serial IRQ interrupts into PCI Express message
signaled interrupts (MSI). classic PCI configuration register space is provided to enable this feature. The
following list identifies the involved configuration registers:
1.
Command register at offset 04h, bit 2 (MASTER_ENB) is asserted (see Section 4.3).
2.
MSI message control register at offset 62h, bits 0 (MSI_EN) and 6:4 (MM_EN) enable single and multiple
MSI messages, respectively (see Section 4.38).
3.
MSI message address register at offsets 64h and 68h specifies the message memory address. A nonzero
address value in offset 68h initiates 64-bit addressing (see Section 4.40).
4.
MSI message data register at offset 6Ch specifies the system interrupt message (see Section 4.41).
5.
Serial IRQ mode control register at offset E0h specifies the serial IRQ bus format (see Section 4.72).
6.
Serial IRQ edge control register at offset E2h selects either level or edge mode interrupts (see
Section 4.73).
7.
Serial IRQ status register at offset E4h reports level mode interrupt status (see Section 4.74).
A PCI Express MSI is generated based on the settings in the serial IRQ edge control register. If the system
is configured for edge mode, then an MSI message is sent when the corresponding serial IRQ interface
sample phase transitions from low to high. If the system is configured for level mode, then an MSI message
is sent when the corresponding IRQ status bit in the serial IRQ status register changes from low to high.
The bridge has a dedicated SERIRQ terminal (T04) for all PCI bus devices that support serialized interrupts.
This SERIRQ interface is synchronous to the PCI bus clock input (CLK) frequency. The bridge always
generates a 17-phase serial IRQ stream. Internally, the bridge detects only 16 IRQ interrupts, IRQ0 frame
through IRQ15 frame. The IOCHCK frame is not monitored by the serial IRQ state machine and never
generates an IRQ interrupt or MSI message.
The multiple message enable (MM_EN) field determines the number of unique MSI messages that are sent
upstream on the PCI Express link. From 1 message to 16 messages, in powers of 2, are selectable. If fewer
than 16 messages are selected, then the mapping from IRQ interrupts to MSI messages is aliased. Table 3−4
illustrates the IRQ interrupt to MSI message mapping based on the number of enabling messages.
Table 3−4. IRQ Interrupt to MSI Message Mapping
IRQ INTERRUPT
1 MESSAGE
ENABLED
2 MESSAGES
ENABLED
4 MESSAGES
ENABLED
8 MESSAGES
ENABLED
16 MESSAGES
ENABLED
IRQ0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
IRQ1
MSI MSG #0
MSI MSG #1
MSI MSG #1
MSI MSG #1
MSI MSG #1
IRQ2
MSI MSG #0
MSI MSG #0
MSI MSG #2
MSI MSG #2
MSI MSG #2
IRQ3
MSI MSG #0
MSI MSG #1
MSI MSG #3
MSI MSG #3
MSI MSG #3
IRQ4
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #4
MSI MSG #4
IRQ5
MSI MSG #0
MSI MSG #1
MSI MSG #1
MSI MSG #5
MSI MSG #5
IRQ6
MSI MSG #0
MSI MSG #0
MSI MSG #2
MSI MSG #6
MSI MSG #6
IRQ7
MSI MSG #0
MSI MSG #1
MSI MSG #3
MSI MSG #7
MSI MSG #7
IRQ8
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #8
IRQ9
MSI MSG #0
MSI MSG #1
MSI MSG #1
MSI MSG #1
MSI MSG #9
IRQ10
MSI MSG #0
MSI MSG #0
MSI MSG #2
MSI MSG #2
MSI MSG #10
IRQ11
MSI MSG #0
MSI MSG #1
MSI MSG #3
MSI MSG #3
MSI MSG #11
IRQ12
MSI MSG #0
MSI MSG #0
MSI MSG #0
MSI MSG #4
MSI MSG #12
IRQ13
MSI MSG #0
MSI MSG #1
MSI MSG #1
MSI MSG #5
MSI MSG #13
IRQ14
MSI MSG #0
MSI MSG #0
MSI MSG #2
MSI MSG #6
MSI MSG #14
IRQ15
MSI MSG #0
MSI MSG #1
MSI MSG #3
MSI MSG #7
MSI MSG #15



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