XIO2000AI datasheet(41/165 Pages) TI

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Feature/Protocol Descriptions

April 2007 Revised October 2008

SCPS155C

The MSI message format is compatible with the PCI Express request header format for 32-bit and 64-bit

memory write transactions. The system message and message number fields are included in bytes 0 and 1

of the data payload.

3.4.6 PCI Bus Clocks

The bridge has seven PCI bus clock outputs and one PCI bus clock input. Up to six PCI bus devices are

supported by the bridge.

Terminal R01 (M66EN) selects the operating frequency of the PCI bus clock outputs. When this input is

asserted high, the PCI bus clocks operate at 66-MHz. When this input is deasserted low, the PCI bus clocks

operate at 33-MHz. The clock control register at offset D8h provides 7 control bits to individually enable or

disable each PCI bus clock output (see Section 4.66). The register default is enabled for all 7 outputs.

The PCI bus clock (CLK) input provides the clock to the internal PCI bus core and serial IRQ core. When the

internal PCI bus clock source is selected, PCI bus clock output 6 (CLKOUT6) is connected to the PCI bus clock

input (CLK). When an external PCI bus clock source is selected, the external clock source is connected to the

PCI bus clock input (CLK). For external clock mode, all seven CLKOUT6:0 terminals must be disabled using

the clock control register at offset D8h (see Section 4.66).

3.5

Quality of Service and Isochronous Features

The bridge has standard and advanced features that provide a robust solution for quality-of-service (QoS) and

isochronous applications. These features are best described by divided them into the following three

categories:

•

PCI port arbitration. PCI port arbitration determines which bus master is granted the next transaction cycle

on the PCI bus. The three PCI port arbitration options are the classic PCI arbiter, the 128-phase, WRR

time-based arbiter, and the 128-phase, WRR aggressive time-based arbiter. The power-up register

default is the classic PCI arbiter. The advanced time-based arbiter features are provided to support

isochronous applications.

•

PCI isochronous windows. There are four separate windows that allow PCI bus-initiated memory

transactions to be labeled with a PCI Express traffic class (TC) beyond the default TC0. Each window

designates a range of PCI memory space that is mapped to a specified TC label. The power-up register

default is all four windows disabled.

•

PCI Express extended VC with VC arbitration. With an extended VC, system software can map a particular

TC to a specific VC. The differentiated traffic on the second VC then uses dedicated system resources

to support a QoS environment. VC arbitration is provided to gate traffic to the upstream PCI Express link.

The three VC arbitration options include strict priority, hardware-fixed round-robin, and 32-phase WRR.

The power-up register default is strict priority with the second VC disabled.

When configuring these standard and advanced features, the following rules must be followed:

The default mode is classic PCI arbiter with the PCI isochronous windows disabled and the second VC

disabled. The bridge performs default PCI bus arbitration without any arbiter-related configuration register

setup.

If a second VC is enabled, then at least one PCI isochronous window must be configured to map upstream

transactions to the second VC.

If a second VC is enabled, then any VC arbiter option interacts with any PCI port arbiter option.

To enable the PCI isochronous windows it is not required to enable a second VC. The memory space to

traffic mapping always uses VC0 for all upstream traffic.

When programming the upstream isochronous window base and limit registers, the 32-bit base/limit

address must be DWORD aligned and the limit address must be greater than the base address.

The following sections describe in detail the standard and advanced bridge features for QoS and isochronous

applications.

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