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XIO2000AI 数据表(PDF) 100 Page - Texas Instruments |
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XIO2000AI 数据表(HTML) 100 Page - Texas Instruments |
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100 / 165 page  Classic PCI Configuration Space 91 April 2007 Revised October 2008 SCPS155C 4.71 Arbiter Time-Out Status Register The arbiter time-out status register contains the status of each request (request 5–0) time-out. The time-out status bit for the respective request is set if the device did not assert FRAME after the arbiter time-out value. See Table 4−45 for a complete description of the register contents. PCI register offset: DEh Register type: Read/Clear Default value: 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 4−45. Arbiter Time-Out Status Register Description BIT FIELD NAME ACCESS DESCRIPTION 7:6 RSVD R Reserved. Returns 00b when read. 5 REQ5_TO RCU Request 5 time-out status 0 = No time-out 1 = Time-out has occurred 4 REQ4_TO RCU Request 4 time-out status 0 = No time-out 1 = Time-out has occurred 3 REQ3_TO RCU Request 3 time-out status 0 = No time-out 1 = Time-out has occurred 2 REQ2_TO RCU Request 2 time-out status 0 = No time-out 1 = Time-out has occurred 1 REQ1_TO RCU Request 1 time-out status 0 = No time-out 1 = Time-out has occurred 0 REQ0_TO RCU Request 0 time-out status 0 = No time-out 1 = Time-out has occurred NOTE:If bit 6 (AUTO_MASK) in the arbiter request mask register (offset DDh, see Section 4.70) is asserted and a PCI bus request time-out is detected, then the request time-out status bits require a special reset sequence. First, the AUTO_MASK bit must be cleared to 0b. Then, the REQ[5:0]_TO bit will clear after a write-back of 1b. |
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