XIO2000AI datasheet(81/165 Pages) TI

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Classic PCI Configuration Space

April 2007 Revised October 2008

SCPS155C

4.50 Device Control Register

The device control register controls PCI Express device specific parameters. See Table 4−26 for a complete

description of the register contents.

PCI register offset:

98h

Read-only, Read/Write

Default value:

2800h

BIT NUMBER

RESET STATE

Table 4−26. Device Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

CFG_RTRY_ENB

Configuration retry status enable. When this read/write bit is set to 1b, the bridge returns a

completion with completion retry status on PCI Express if a configuration transaction forwarded

to the secondary interface did not complete within the implementation specific time-out period.

When this bit is set to 0b, the bridge does not generate completions with completion retry status

on behalf of configuration transactions. The default value of this bit is 0b.

14:12

MRRS

Maximum read request size. This field is programmed by host software to set the maximum size

of a read request that the bridge can generate. The bridge uses this field in conjunction with the

cache line size register (offset 0Ch, see Section 4.6) to determine how much data to fetch on a

read request. This field is encoded as:

000 = 128B

001 = 256B

010 = 512B (default)

011 = 1024B

100 = 2048B

101 = 4096B

110 = Reserved

111 = Reserved

ENS

Enable no snoop. Controls the setting of the no snoop flag within the TLP header for upstream

memory transactions mapped to any traffic class mapped to a virtual channel (VC) other than

VC0 through the upstream decode windows.

0 = No snoop field is 0b

1 = No snoop field is 1b (default)

10k

APPE

Auxiliary power PM enable. This bit has no effect in the bridge.

0 = AUX power is disabled (default)

1 = AUX power is enabled

PFE

Phantom function enable. Since the bridge does not support phantom functions, this bit is

read-only 0b.

ETFE

Extended tag field enable. Since the bridge does not support extended tags, this bit is read-only

0b.

7:5

MPS

Maximum payload size. This field is programmed by host software to set the maximum size of

posted writes or read completions that the bridge can initiate. This field is encoded as:

000 = 128B (default)

001 = 256B

010 = 512B

011 = 1024B

100 = 2048B

101 = 4096B

110 = Reserved

111 = Reserved

ERO

Enable relaxed ordering. Since the bridge does not support relaxed ordering, this bit is read-only

0b.

kThis bit is sticky and must retain its value when the bridge is powered by VAUX.

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