 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
XIO2000AI 数据表(PDF) 127 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
XIO2000AI 数据表(HTML) 127 Page - Texas Instruments |
|
|
127 / 165 page  Memory-Mapped TI Proprietary Register Space 118 April 2007 Revised October 2008 SCPS155C 6 Memory-Mapped TI Proprietary Register Space The programming model of the memory-mapped TI proprietary register space is unique to this device. These custom registers are specifically designed to provide enhanced features associated with upstream isochronous applications. All bits marked with a k are sticky bits and are reset by a global reset (GRST) or the internally-generated power-on reset. All bits marked with a † are reset by a PCI Express reset (PERST), a GRST or the internally-generated power-on reset. The remaining register bits are reset by a PCI Express hot reset, PERST, GRST, or the internally-generated power-on reset. Table 6−1. Device Control Memory Window Register Map REGISTER NAME OFFSET Upstream isochrony capabilities Revision ID Device control map ID 00h Reserved Upstream isochrony control 04h Reserved Upstream isochronous window 0 control 08h Upstream isochronous window 0 base address 0Ch Upstream isochronous window 0 limit 10h Reserved Upstream isochronous window 1 control 14h Upstream isochronous window 1 base address 18h Upstream isochronous window 1 limit 1Ch Reserved Upstream isochronous window 2 control 20h Upstream isochronous window 2 base address 24h Upstream isochronous window 2 limit 28h Reserved Upstream isochronous window 3 control 2Ch Upstream isochronous window 3 base address 30h Upstream isochronous window 3 limit 34h Reserved 38h−3Ch GPIO data† GPIO control† 40h Serial-bus control and status† Serial-bus slave address† Serial-bus word address† Serial-bus data† 44h Serial IRQ edge control† Reserved Serial IRQ mode control† 48h Reserved Serial IRQ status 4Ch † One or more bits in this register are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset. 6.1 Device Control Map ID Register The device control map ID register identifies the TI proprietary layout for this device control map. The value 01h identifies this as a PCI Express-to-PCI bridge supporting upstream isochronous capabilities. Device control memory window register offset: 00h Register type: Read-only Default value: 01h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 1 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
