XIO2000AI datasheet(134/165 Pages) TI

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Memory-Mapped TI Proprietary Register Space

125

April 2007 Revised October 2008

SCPS155C

6.17 GPIO Control Register

This register controls the direction of the eight GPIO terminals. This register has no effect on the behavior of

GPIO terminals that are enabled to perform secondary functions. The secondary functions share GPIO0

(CLKRUN), GPIO1 (PWR_OVRD), GPIO4 (SCL), and GPIO5 (SDA). This register is an alias of the GPIO

control register in the classic PCI configuration space (offset B4h, see Section 4.59). See Table 6−8 for a

complete description of the register contents.

Device control memory window register offset:

40h

Read-only, Read/Write

Default value:

0000h

BIT NUMBER

RESET STATE

Table 6−8. GPIO Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:8

RSVD

Reserved. Returns 00h when read.

7†

GPIO7_DIR

GPIO 7 data direction. This bit selects whether GPIO7 is in input or output mode.

0 = Input (default)

1 = Output

6†

GPIO6_DIR

GPIO 6 data direction. This bit selects whether GPIO6 is in input or output mode.

0 = Input (default)

1 = Output

5†

GPIO5_DIR

GPIO 5 data direction. This bit selects whether GPIO5 is in input or output mode.

0 = Input (default)

1 = Output

4†

GPIO4_DIR

GPIO 4 data direction. This bit selects whether GPIO4 is in input or output mode.

0 = Input (default)

1 = Output

3†

GPIO3_DIR

GPIO 3 data direction. This bit selects whether GPIO3 is in input or output mode.

0 = Input (default)

1 = Output

2†

GPIO2_DIR

GPIO 2 data direction. This bit selects whether GPIO2 is in input or output mode.

0 = Input (default)

1 = Output

1†

GPIO1_DIR

GPIO 1 data direction. This bit selects whether GPIO1 is in input or output mode.

0 = Input (default)

1 = Output

0†

GPIO0_DIR

GPIO 0 data direction. This bit selects whether GPIO0 is in input or output mode.

0 = Input (default)

1 = Output

† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

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