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VG6640 数据表(PDF) 60 Page - STMicroelectronics |
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VG6640 数据表(HTML) 60 Page - STMicroelectronics |
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60 / 126 page ![]() Control interface VG6640, VD6640 60/126 DocID023597 Rev 11 0x2491 HDRLMS_control 8UI 0x02 RW [5] - EnableFlash: 1 = Enable flash repair mode [4] - Refstream: 0 = Long12 1 = Medium [3] - DecideOnShort: 0 = Luma comparisons made on LongMedium 1 = Luma comparisons made on Short [2:0] - MergeMode: 0 = Linearise 1 = Merge only 2 = Merge/Linearize 3 = Grad to add 4 = Grad to merge 0x2492 PWL_control 8UI 0x01 RW [1] - PWLBypassMode: 0 = MSB only 1 = LSB only [0] - PWLEnable: 1 = PWL enabled Table 26. Gain merge compensation control registers [0x248B - 0x2492] (continued) Index Byte Register name Data type Default Type Comment |
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