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VG6640 数据表(PDF) 92 Page - STMicroelectronics |
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VG6640 数据表(HTML) 92 Page - STMicroelectronics |
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92 / 126 page  Electrical characteristics VG6640, VD6640 92/126 DocID023597 Rev 11 9.9 I2C interface - SDA, SCL Table 51. I2C interface - signal characteristics Symbol C Parameter Minimum Typical Maximum Unit VSL T Low level input voltage (SDA, SCL) -0.5 0.5 V VSH T High level input voltage (SDA, SCL) 1.3 2.3 V CO T Capacitive load on SCL or SDA 550 pF ISL P Input leakage current(1) (SDA, SCL) 1. For 0.1 x VDIG ≤VSL ≤0.9 x VDIG -10 10 µA ISDAF D SDA output sink current (Fast mode) 4mA ISDAFP D SDA output sink current (Fast+ mode) 20 mA VOL T SDA output voltage low level (Fast+ mode, 20mA, VDIG=1.8V) 0.4 V VOL T SDA output voltage low level (Fast+ mode, 20mA, VDIG=2.8V) 0.4 V Table 52. I2C interface - timing characteristics Symbol C Parameter Minimum Typical Maximum Unit tSCL T SCL clock frequency 1000(1) 1. To achieve the maximum 1MHz SCL rate on a bus with worst case capacitance it is required that the EXTCLK_XTAL1 input is driven with a clock of at least 19MHz frequency. kHz tLOW T Clock pulse width low 0.5 µs tHIGH T Clock pulse width high 0.26 µs tSP T Pulse width of spikes which are suppressed by the input filter 050 ns tBUF T Bus free time between transmissions 0.5 µs tHD.STA T Start hold time 0.26 µs tSU.STA T Start set-up time 0.26 µs tSU.DAT T Data in set-up time 50 ns tHD.DAT T Data in hold time 16 ns tVD.DAT T Data out valid time 0.45 µs tR T SCL/SDA rise time 120 ns tF T SCL/SDA fall time 120 ns tSU.STO Stop set-up time 0.26 µs |
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