VG6640 datasheet(69/126 Pages) STMICROELECTRONICS

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DocID023597 Rev 11

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VG6640, VD6640

Video data interface

125

Data synchronization methods

External capture systems may synchronize with the data output using ITU-R BT.601

compatible hardware synchronization signals, consisting of horizontal sync (HSYNC) and

vertical sync (VSYNC).

The synchronization signals can be configured to meet the needs of the companion device.

Pixel clock (PIX-CLK)

The pixel clock is programmable such that data may be clocked on the rising or falling edge

of the pixel clock.

5.2.2

Frame format - hardware synchronization

The image sensor provides two programmable hardware synchronization signals: VSYNC

and HSYNC. The position of these signals within the image frame is automatically set so

that the signals track the active video portion of the output frame regardless of its size.

Figure 17. Hardware synchronization frame structure

VSYNC

Visible pixel data

Header embedded data lines

Inter-frame blanking

(active lines)

Inter-

line

blanking

time

(shown

vertically)

time

HSYNC signal

signal

Note: The polarity of HSYNC and/or VSYNC may be reversed

Trailer embedded data lines

ASIL data lines

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