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VG6640 数据表(PDF) 38 Page - STMicroelectronics |
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VG6640 数据表(HTML) 38 Page - STMicroelectronics |
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38 / 126 page  Control interface VG6640, VD6640 38/126 DocID023597 Rev 11 4.2.5 Video timing registers [0x0300 to 0x0387] Table 10. Video timing registers [0x0300 to 0x0387] Index Byte Register name Data type Default Type Comment 0x0300 HI VT_Pix_Clk_Div 16UI 0x00 RW Video timing pixel clock divider. Min = 1 Max = 8 0x0301 LO 0x06 0x0302 HI VT_Sys_Clk_Div 16UI 0x00 RW Video timing system clock divider. Min = 1 Max = 8 0x0303 LO 0x01 0x0304 HI Pre_PLL_Clk_Div 16UI 0x00 RW Pre PLL clock divider value. Valid values = 1, 2, 4, 8 0x0305 LO 0x02 0x0306 HI PLL_Multiplier 16UI 0x00 RW PLL multiplier value. Min = 37 Max = 167 0x0307 LO 0x84 0x0308 HI Op_Pix_Clk_Div 16UI 0x00 RW Output timing pixel clock divider. Valid value = 8 0x0309 LO 0x08 0x030A HI Op_Sys_Clk_Div 16UI 0x00 RW Output timing pixel clock divider. Min = 1 Max = 4 0x030B LO 0x01 0x0310 HI ExtClk_Frequency_MHz 16UR 0x0C RW External clock frequency. This register must be set to the value of the clock applied to the EXTCLK_XTAL1 pin. 0x0311 LO 0x00 0x0340 HI Frame_Length_Lines _Status 16UI 0x03 DNW Length of the video frame in lines Min = 159 Max = 65536. 0x0341 LO 0xFC 0x0342 HI Line_Length_PCK 16UI 0x05 RW Length of a line of video in pixels. Min = 1438 (21.8uS @ 66MHz Pixel Clock) Max = 65536 0x0343 LO 0x9E 0x0344 HI X_Addr_Start 16UI 0x00 RW X pixel address of the top left corner of the visible pixel data. Min = 0 Max = 1303 0x0345 LO 0x00 0x0346 HI Y_Addr_Start 16UI 0x00 RW Y line address of the top left corner of the visible pixel data. Min = 0 Max = 979 0x0347 LO 0x00 0x0348 HI X_Addr_End 16UI 0x05 RW X pixel address of the bottom right corner of the visible pixel data. Min = 0 Max = 1303 0x0349 LO 0x17 |
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