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VG6640 数据表(PDF) 71 Page - STMicroelectronics |
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VG6640 数据表(HTML) 71 Page - STMicroelectronics |
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71 / 126 page ![]() DocID023597 Rev 11 71/126 VG6640, VD6640 Video timing 125 6 Video timing This chapter should be read in conjunction with the section on video timing found within the SMIA Functional Specification (Section 5 - Video Timing). The following video timing features are supported: • external synchronization of frame start using an I2C command or a hardware signal • single region windowing (window of interest) • dual register banks are available in firmware to allow per frame context switching between different timing sets • subsampling of pixel data • programmable line and frame blanking • vertical and/or horizontal image mirroring 6.1 Programmable image size The native size of the pixel array is 1304 x 980. A region of the pixel array may be defined by programming the x_addr_start, y_addr_start, x_addr_end and y_addr_end registers. The addressed region of the array is used in any subsequent subsampling. The x_output_size and y_output_size registers are not intended as the primary cropping controls. They are intended to define the position of the frame end(a) so that the sensor does not need to calculate this based on the window of interest, digital crop or sub-sampling settings. The companion device should set the output sizes to exactly enclose the output image data. If the companion device does not do this, the image sensor will treat the output sizes as being calculated from the top left hand corner of the output array. If the programmed output sizes are smaller than the output data size, the output data is cropped from the bottom and right limits. If the programmed output sizes are larger than the output data, the additional data lines are padded out to the defined output size with undefined data. a. In the case of CSI-2 output interface, the frame end is marked by the FE code, refer to Figure 16: CSI-2 frame format on page 67. In the case of the parallel output interface, the frame end is marked by the VSYNC transition, refer to Figure 17: Hardware synchronization frame structure on page 69. |
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