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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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VG6640 数据表(PDF) 74 Page - STMicroelectronics |
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VG6640 数据表(HTML) 74 Page - STMicroelectronics |
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74 / 126 page  Video timing VG6640, VD6640 74/126 DocID023597 Rev 11 Figure 20. 2 x 2 subsampling readout example (Bayer) 1. Figure 20 valid only for RGB 6.3 External clock to pixel clock relationship The image sensor has a clock generation block which contains a PLL (phase locked loop). This block generates all the necessary internal clocks from a single external clock input. Changes to the PLL settings on the image sensor will only be consumed when they are changed during standby. Figure 21 shows the internal functional blocks, which define the relationship between the external input clock frequency and the pixel clock frequency. The majority of the logic within the device is clocked by VT_PixelClock including the 12bit ITU interface if selected. If the CSI2 interface is used then the data rate is defined by OpClock giving a bit rate on the CSI2 interface of OpClock bytes or a maximum of 66MHz * 8bits = 528Mbits/sec When the device is not streaming the PLL is bypassed and the internal digital logic, including the I2C block, is clocked directly from the EXTCLK_XTAL1 input clock. 8 5 6 7 G Gr R B G Gr R B G Gr R B G Gr R B G Gr R B G Gr R B G Gr R B G Gr R B G Gr R B 4 1 2 3 9 10 8 567 4 12 3 9 010 0 11 1 33 3 1 1 1 3 3 3 Example: x_even_inc=1 x_odd_inc=3 y_even_inc=1 y_odd_inc=3 |
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