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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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VG6640 数据表(PDF) 95 Page - STMicroelectronics |
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VG6640 数据表(HTML) 95 Page - STMicroelectronics |
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95 / 126 page  DocID023597 Rev 11 95/126 VG6640, VD6640 Electrical characteristics 125 9.11 Parallel (ITU) interface Table 57. Parallel interface - signal characteristics Symbol C Parameter Conditions Minimum Typical Maximum Unit VOL C Output low level -IOL = 4 mA 0.15 V VOH C Output high level IOH = 4 mA 1.65 V Table 58. Parallel interface - timing characteristics Symbol C Parameter Conditions Minimum Typical Maximum Unit fPIXCLK T PIXCLK frequency Load capacitanc e CL = 15pF 66.5 MHz DPIXCLK T PIXCLK duty cycle 43 50 58 % tRCLK T PIXCLK rise time (20 - 80%) 1.3 2.0 ns tFCLK T PIXCLK fall time (80 - 20%) 1.2 1.7 ns tRDATA T DOUT[11:0], VSYNC, HSYNC rising (20 - 80%) Normal drive(1) 23.1 ns T Low drive 2.5 3.8 ns tFDATA T DOUT[11:0], VSYNC, HSYNC falling (80 - 20%) Normal drive 2 3.1 ns T Low drive 2.5 3.6 tRDV T PIX-CLK rising (50%) to output data valid (20% or 80%) Normal drive 1.4 4.6 9.0 ns Low drive 2.1 6.3 11.5 1. Normal drive and low drive modes are selected by writing to register ParOutIF_Drive (0x24A2). |
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