VG6640 datasheet(15/126 Pages) STMICROELECTRONICS

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DocID023597 Rev 11

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VG6640, VD6640

Signal, ball assignment, pad, and wafer description

125

SCL

I2C-style clock

VDIG

FSYNC_IN

I-PD5

Frame synchronization input (rising edge)

VDIG

FSYNC_OUT

Frame synchronization output (start of integration on

rising edge)

VDIG

ECC_OUT

Flags uncorrectable (double bit) ECC occurrences

VDIG

GPIO

I/O

General purpose input or output / Flicker Indication

VDIG

Test interface

JTAG_TMS

I-PD5

Test mode (connect to GND when not in use)

VDIG

JTAG_TCK

I-PD5

Test clock (connect to VDIG when not in use)

VDIG

JTAG_TDI

I-PD5

Test data in (connect to GND when not in use)

VDIG

JTAG_TDO

Test data out

VDIG

Other pins

Leave unconnected

N/A

1. I = Input, O = Output, I/O = Input or output, I-PD5 -= Input with 5K pull-down, I-SCH = Input with Schmitt trigger, I-Sh-PU20

= Input Schmitt with 20k pull-up, REF = Reference, PWR = Power supply or ground

2. LO = Digital low level, HI = Digital high level, HI_Z = High impedance state

Table 4. Signal description with Im2BGA 100 balls (continued)

Pin name

Type(1)

Description

Reset

state(2)

Reference

supply

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