VG6640 datasheet(10/126 Pages) STMICROELECTRONICS

10 / 126 page

Overview

VG6640, VD6640

10/126

DocID023597 Rev 11

1.1

Interfaces

The image sensor is ready to connect to the camera enabled companion device. Image data

is output from the image sensor over a 12-bit parallel interface or a dual lane MIPI CSI-2

serial interface. Before transmission, the image data is compressed from 22-bit to 12-bit

using a compression algorithm that causes no perceptible losses.

The 12-bit parallel interface is capable of 66 Mpixel/s.

The dual lane MIPI CSI-2 serial data interface is capable of 2 x 550 Mbit/s and is the

industry standard for low EMI and excellent EMC.

The control interface is I2C in either Fast (up to 400KHz) or Fast+ (up to 1MHz) modes.

1.2

Power supplies

Power supplies required:

•

2.8 V for the analog blocks

•

1.8 V for the digital I/Os

•

1.2 V for the digital core

The internal digital core operates from 1.2V. This may optionally be supplied from an

external regulator or generated internally from the 1.8V supply by a low drop out regulator

included in the image sensor.

1.3

Clock and PLL

An input clock is required which can be supplied as an external clock in the range of 12 MHz

to 50 MHz or as an external quartz crystal of 12 MHz to 27 MHz.

The image sensor has an embedded phased locked loop (PLL) block to generate all

necessary internal clocks. The PLL can be configured to run at a fixed frequency or with a

spread spectrum of up to 30 kHz modulation.

VG6640 数据表(PDF) 10 Page - STMicroelectronics