VG6640 datasheet(90/126 Pages) STMICROELECTRONICS

90 / 126 page

Electrical characteristics

VG6640, VD6640

90/126

DocID023597 Rev 11

9.5

System clock

Table 44. Maximum current consumption while streaming

Mode 1

Mode 2

Mode 3

Mode 4

Mode5

Conditions(1)

1. Mode 1 VDIG = 2.8 V, 12 MHz external clock, tested at 25 °C junction temperature

Modes 2, 3, 4, and 5 VDIG = 1.8 V, 12 MHz external clock, tested at 25 °C junction temperature

Worst case

Standard

Low power

Night mode

Very low

power

CCCCC

VCORE (mA)

VDIG (mA)

200

150

VANA (mA)

140

150

140

Table 45. EXTCLK_XTAL1 - characteristics

Symbol

Parameter

Minimum

Maximum

Unit

VEXTCLKL

DC-coupled square wave low level input

-0.5

0.5

VEXTCLKH

DC-coupled square wave high level input

1.3

2.3

fEXTCLK

Clock frequency input

MHz

IEXTCLKL

Input leakage current(1)

1. For VGND ≤VEXTCLK ≤VDIG

µA

Table 46. System clock - crystal

Symbol

Parameter

Minimum

Maximum

Unit

fXTAL

Crystal resonant frequency

12(tbc)

27(tbc)

MHz

Table 47. PLL timing characterics

Symbol

Parameter

Minimum

Maximum

Unit

fPLLINPUT

PLL input frequency

(after internal pre-divider)

612

MHz

tJITTER

Maximum allowable clock jitter on input to

PLL

100

fPLLOUTPUT

PLL output frequency

(after fixed divide by 2)

225

500

MHz

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