ADAV803ASTZ datasheet(30/56 Pages) AD

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ADAV803

Rev. 0 | Page 30 of 56

gisters is eight bits wide. Where bits are described as reserved

these bits should be programmed as zero.

I2C INTERFACE

The I2C interface of the ADAV803 is a 2-wire interface

consisting of a clock line, SCL, and a data line, SDA. SDA is

bidirectional; the ADAV803 drives SDA to either acknowledge

the master, ACK, or send data during a read operation. The SDA

pin for the I2C port is an open-drain collector that requires a 1

kΩ pull-up resistor. A write or read access occurs when the SDA

line is pulled low while the SCL line is high, indicated by START

in the timing diagrams. SDA is allowed to change only when

SCL is low, except when a start or stop condition occurs, as

shown in Figure 53 and Figure 54. The I2C interface supports

both standard (100 kbps) and fast (400 kbps) modes as defined

by the I2C standards.

The first eight bits of the access consist of the device address

and the R/W bit. The device address consists of an internal

built-in address (0b00100) and two address pins, AD1 and AD0.

The two address pins allow up to four ADAV803s to be used in

a system.

write operation to the ADAV803 involves sending a

start condition and then sending the device address with the

R/W set low. The ADAV803 responds by issuing an ACK to

indicate that it has been addressed. The user then sends a

second frame telling the ADAV803 which register is required to

be written to. The 7-bit register address is left-shifted to make

the eight bits that the frame requires. Another ACK is issued by

the ADAV803. Finally the user can send another frame with the

eight data bits required to be written to the register. A third

ACK is issued by the ADAV803, after which the user can send a

stop condition to complete the data transfer.

A read operation requires that the user first write to the

ADAV803 to point to the correct register and then read the

data. This is achieved by sending a start condition followed by

the device address frame, with R/W low, and then the register

address frame. Following the ACK from the ADAV803, the user

must issue a repeated start condition. This is identical to a start

condition. The next frame is the device address with R/W set

high. On the next frame, the ADAV803 outputs the register data

on the SDA line. A stop condition completes the read operation.

Figure 53 and Figure 54 show examples of writing to and read-

ing from the DAC left volume register (Address 0b1101000).

INTERFACE CONTROL

The ADAV803 has a dedicated control port to allow the internal

registers of the ADAV803 to be accessed. Each of the intern

Initiating a

(RES),

SCK

SDA

AD1

AD0

R/W

START BY

MASTER

ACK. BY

ADAV803

ACK. BY

ADAV803

ACK. BY

ADAV803

STOP BY

MASTER

FRAME 1

CHIP ADDRESS BYTE

SCK

(CONTINUED)

SDA

(CONTINUED)

FRAME 2

FRAME 3

DATA BYTE TO

ADAV803

Figure 53. Writing to the DAC Left Volume Register in I2C

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