ADAV803ASTZ datasheet(6/56 Pages) AD

6 / 56 page

ADAV803

Rev. 0 | Page 6 of 56

Parameter

Min

Typ

Max

Unit

Comments

Power-Down Current

RESET low, no MCLK

Analog Current

Digital Current

2.5

Digital Interface Current

700

µA

DIRIN/DIROUT Current

3.5

PLL Current

900

µA

Power Supply Rejection

Signal at Analog Supply Pins

−70

1 kHz, 300 mV p-p

−70

20 kHz, 300 mV p-p

1 Guaranteed by design.

TIMING SPECIFICATIONS

Timing specifications are guaranteed over the full temperature and supply range.

Table 3.

Parameter

Min

Typ

Max

Unit

Comments

MASTER CLOCK AND RESET

fMCLK

MCLKI Frequency

12.288

MHz

fXIN

XIN Frequency

MHz

tRESET

RESET Low

I2C PORT

fSCL

SCL Clock Frequency

400

kHz

tSCLH

SCL High

0.6

µs

tSCLL

SCL Low

1.3

µs

Start Condition

tSCS

Setup Time

0.6

µs

Relevant for repeated start condition

tSCH

Hold Time

0.6

µs

After this period, the first clock is generated

tDS

Data Setup Time

100

tSCR

SCL Rise Time

300

tSCF

SCL Fall Time

300

tSDR

SDA Rise Time

300

tSDF

SDA Fall Time

300

Stop Condition

tSCS

Setup Time

0.6

µs

SERIAL PORTS1

Slave Mode

tSBH

xBCLK High

tSBL

xBCLK Low

fSBF

xBCLK Frequency

64 × fS

tSLS

xLRCLK Setup

To xBCLK rising edge

tSLH

xLRCLK Hold

From xBCLK rising edge

tSDS

xSDATA Setup

To xBCLK rising edge

tSDH

xSDATA Hold

From xBCLK rising edge

tSDD

xSDATA Delay

From xBCLK falling edge

ADAV803ASTZ 数据表(PDF) 6 Page - Analog Devices

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