ADAV803ASTZ datasheet(32/56 Pages) AD

32 / 56 page

ADAV803

Rev. 0 | Page 32 of 56

17. SRC and Cl

Control Register

SRCDIV0

CLK2DIV1

CLK2DIV0

CLK1DIV1

CLK1DIV0

MCLKSEL1

MCLKSEL0

Table

ock

SRCDIV

ADDRESS = 0000000 (0x00)

SRCDIV1–0

Divides the SRC master clock.

00 = SRC master clock is not divided.

is divided by 1.5.

k is divided by 3.

er for Internal Clock 2 (ICLK2).

Clock divider for Internal Clock 1 (ICLK1).

00 = Divide by 1.

ivide by

= Divide by

lection for the SRC master clock.

12 × fS).

ck (256 × fS).

01 = SRC master clock

10 = SRC master clock is divided by 2.

11= SRC master cloc

CLK2DIV1–0

Clock divid

00 = Divide by 1.

01 = Divide by 1.5.

10 = Divide by 2.

11 = Divide by 3.

CLK1DIV1–0

01 = Divide by 1.5.

10 = D

MCLKSEL1–0

Clock se

00 = Internal Clock 1.

01 = Internal Clock 2.

10 = PLL recovered clock (5

11 = PLL recovered clo

Table 18. SPDIF Loop

RES

TxMUX

back Control Register

RES

ADDRESS = 0000011 (0x03)

TxMUX

Selects the source for SPDIF output (DITOUT).

0 = SPDIF transmitter, normal mode.

1 = DIRIN, loopback mode.

Table 19. Playback Port Control Register

RES

CLKSRC1

CLKSRC0

SPMODE2

SPMODE1

SPMODE0

ADDRESS = 0000100 (0x04)

CLKSRC1–0

Selects the clock source for generating the ILRCLK and IBCLK.

00 = Input port is a slave.

01 = Recovered PLL clock.

10 = Internal Clock 1.

11 = Internal Clock 2.

SPMODE2–0

Selects the serial format of the playback port.

000 = Left-justified.

001 = I2S.

100 = 24-bit, right-justified.

101 = 20-bit, right-justified.

110 = 18-bit, right-justified.

111 = 16-bit, right-justified.

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