ADAV803ASTZ datasheet(55/56 Pages) AD

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ADAV803

Rev. 0 | Page 55 of 56

LAYOUT CONSIDERATIONS

Getting the best performance from the ADAV803 requires a

careful layout of the printed circuit board (PCB). Using separate

analog and digital ground planes is recommended, because

these give the currents a low resistance path back to the power

supplies. The ground planes should be connected in only one

place, usually under the ADAV803, to prevent ground loops.

The analog and digital supply pins should be decoupled to their

respective ground pins with a 10 µF to 47 µF tantalum capacitor

and a 0.1 µF ceramic capacitor. These capacitors should be

placed as close as possible to the supply pins.

ADC

The

itch capacitor input stage and is, therefore,

particularly sensitive to digital noise. Sources of noise, such as

PLLs or clocks, should not be routed close to the ADC section.

The CAPxN and CAPxP pins form a charge reservoir for the

switched capacitor section of the ADC, so keeping these nodes

electrically quiet is a key factor in ensuring good performance.

The capacitors connected to these pins should be of good

quality, either NPO or COG, and should be placed as close as

possible to CAPxN and CAPxP.

DAC

The DAC requires an analog filter to filter out-of-band noise

from the analog output. A third-order Bessel filter is

recommended, although the filter to use depends on the

requirements of the application.

PLL

The PLL can be used to generate digital clocks, either for use

internally or to clock external circuitry. Because every clock is a

potential source of noise, care should be taken when using the

it is recommended that the outputs be disabled. To reduce

cross-coupling between clocks, a digital ground trace can be

routed on either side of the PLL clock signal, if required.

The PLL has its own power supply pins. To get the best

performance from the PLL and from the rest of the ADAV803,

it is recommended that a separate analog supply be used. Where

this is not possible, the user must decide whether to connect the

PLL supply to the analog (AVDD) or digital (DVDD) supply.

Connecting the PLL supply to AVDD gives the best jitter

performance, but can degrade the performance of the ADC and

DAC sections slightly due to the increased digital noise created

on the AVDD by the PLL. Connecting the PLL supply to DVDD

keeps digital noise away from the analog supply, but the jitter

specifications might be reduced depending on the quality of the

digital supply. Using the layout recommendations described in

this section helps to reduce these effects.

RESET AND POWER-DOWN CONSIDERATIONS

When the ADAV803 is held in reset by bringing the RESET

ADC uses a sw

PLL. The ADAV803’s PLL outputs can be enabled or disabled, as

required. If the PLL clocks are not required by external circuitry,

pin low, a number of circuit blocks remain powered up. For

example, the crystal oscillator circuit based around the XIN

and XOUT pins is still active, so that a stable clock source

is available when the ADAV803 is taken out of reset. Also, the

VCO associated with the SPDIF receiver is active so that the

receiver locks to the incoming SPDIF stream in the shortest

possible time. Where power consumption is a concern, the

individual blocks of the ADAV803 can be powered down via

the control registers to gain significant power savings. Table 82

shows typical power savings when using the power-down bits

in the control registers.

Table 82. Typical Power Requirements

Operating

Mode

AVDD

(mA)

DVDD

(mA)

ODVDD

(mA)

DIR_VDD

(mA)

Power

(mW)

Normal

280.5

Reset low

2.5

123.75

Power-down

bits

0.1

1.3

0.7

46.53

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