ADAV803ASTZ datasheet(22/56 Pages) AD

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ADAV803

Rev. 0 | Page 22 of 56

LL SECTION

n to generate

The ADAV803 features a dual PLL configuratio

independent system clocks for asynchronous operation.

Figure 37 shows the block diagram of the PLL section. The PL

generates the internal and system clocks from a 27 MHz cloc

This clock is generated either by a crystal connected between

XIN and XOUT, as shown in Figure 35, or from an external

clock source connected directly to XIN. A 54 MHz clock can

also be used, if the internal clock divider is used.

XTAL

Figure 35. Crystal Connection

Both PLLs (PLL1 and PLL2) can be programmed independentl

and can accommodate a range of sampling rates (32/44.1/48

kHz) with selectable system clock oversampling rates of 256 and

384. Higher oversampling rates can also be selected by enabling

the doubling of the sampling rate to give 512 or 768 × f

The PLL outputs can b

o act as clock sources

for the other component blocks such as the ADC, DAC, and so

on. The outputs of the PLLs are also available on the three

SYSCLK pins. Figure 38 shows how the PLLs can be configured

to provide the sampling clocks.

Table 7. PLL Frequency Selection Options

ratios.

Note that this option also allows oversampling ratios of 256 o

384 at double sample rates of 64/88.2/96 kHz.

e routed internally t

MCLK Selection

PLL

Sample Rate (fS)

Normal fS

Double fS

32/44.1/48 kHz

256/384 × fS

512/768 × fS

64/88.2/96 kHz

256/384 × fS

32/44.1/48 kHz

256/384 × f

512/768 × f

64/88.2/96 kHz

256/384 × fS

Same as fS selected

512 × fS

For PLL 2A

512 × fS

The PLLs require some external components to operate

correctly. These components, shown in Figure 36, form a loop

filter that integrates the current pulses from a charge pump an

produces a voltage that is used to tune the VCO. Good quali

capacitors, such as PPS fi

lm, are recommended. Figure 37 shows

a block diagram of the PLL sect n, including master clock

selection. Figure 3

ncies at the

al PLL

locks

ould be

filter pins.

8 shows how the clock freque

clock output pins, SYSCLK1 to SYSCLK 3, and the intern

clock values, PLL1 and PLL2, are selected.

The clock nodes, PLL1 and PLL2, can be used as master c

for the other blocks in the ADAV803 such as the DAC or ADC.

The PLL has separate supply and ground pins, which sh

as clean as possible to prevent electrical noise from being

converted into clock jitter by coupling onto the loop

PLL BLOCK

PLL_LFx

3.3

Ω

100nF

AVDD

6.8nF

Figure 36. PLL Loop Filter

MCLKI

MCLKO

XOUT

XIN

REG 0x74

BIT 5

REG 0x74

BIT 4

REG 0x78

BIT 6

REG 0x78

BIT 7

PHASE

DETECTOR

AND LOOP

FILTER

PLL_LF1

PLL1

SYSCLK1

PLL_LF2

SYSCLK2

SYSCLK3

÷2

VCO

÷N

OUTPUT

SCALER N1

PHASE

DETECT

AND LO

FILTE

PLL2

VCO

÷N

OUTPUT

SCALER N2

OUTPUT

SCALER N3

Figure 37. PLL Section Block Diagram

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