ADAV803ASTZ datasheet(35/56 Pages) AD

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ADAV803

Rev. 0 | Page 35 of 56

OCK

RxCLK1–

Table 24. Receiver Configuration 1 Register

NOCL

TO_ DEEMPH

ERR1–0

LOCK1–0

6, 5

3, 2

1, 0

ADDRESS = 0001001 (0x09)

NOCLOCK

Selects the source of the receiver clock when the PLL is not locked.

clock.

ata from the receiver based on the channel status information.

should take, if the receiver detects a parity or biphase error.

OCK1–0

tion the receiver should take, if the PLL loses lock.

11 = Soft-mute of the last valid audio sample.

0 = Recovered PLL clock is used.

1 = ICLK1 is used.

RxCLK1–0

Determines the oversampling ratio of the recovered receiver clock.

00 = RxCLK is a 128 × fS recovered clock.

01 = RxCLK is a 256 × fS recovered clock.

10 = RxCLK is a 512 × fS recovered

11 = Reserved.

AUTO_DEEM

Automatically de-emphasizes the d

0 = Automatic de-emphasis is disabled.

1 = Automatic de-emphasis is enabled.

ERR1–0

Defines what action the receiver

00 = No action is taken.

01 = Last valid sample is held.

10 = Invalid sample is replaced with zeros.

11 = Reserved.

Defines what ac

00 = No action is taken.

01 = Last valid sample is held.

10 = Zeros are sent out after the last valid sample.

Table 25. Receiver Co

ration 2 Register

SP_PL

SP_PLL_ SEL

RES

NO NONAUDIO

NO_VALIDITY

nfigu

RxMUTE

1–0

5, 4

ADDRESS = 0001010 (0x0A)

RxMUTE

Hard-mutes the audio output for the AES3/SPDIF receiver.

0 = AES3/SPDIF receiver is not muted.

1 = AES3/SPDIF receiver is muted.

SP_PLL

AES3/SPDIF receiver PLL accepts a left/right clock from one of the four serial ports as the PLL reference clock.

ES3/SPDIF preambles is the reference clock to the PLL.

ports is the reference clock to the PLL.

reference clock to the PLL when SP_PLL is set.

NONAUDIO

er is not allowed into the sample rate converter

efined by the IEC61937 standard, then the data from

receiver is not allowed into the SRC regardless of the state of this bit.

the SRC.

s not allowed into the SRC, if the NONAUDIO bit is set.

the AES3/SPDIF receiver is not allowed into the SRC.

0 = AES3/SPDIF receiver data is sent to the SRC.

1 = Data from the AES3/SPDIF receiver is not allowed into the SRC, if the VALIDITY bit is set.

0 = Left/right clock generated from the A

1 = Left/right clock from one of the serial

SP_PLL_SEL1–0

Selects one of the four serial ports as the

00 = Playback port is selected.

01 = Auxiliary input port is selected.

10 = Record port is selected.

11 = Auxiliary output port is selected.

When the NONAUDIO bit is set, data from the AES3/SPDIF receiv

NAUDIO data is due to DTS, AAC, and so on, as d

(SRC). If the NO

the AES3/SPDIF

0 = AES3/SPDIF receiver data is sent to

1 = Data from the AES3/SPDIF receiver i

NO_VALIDITY

When the VALIDITY bit is set, data from

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