ADAV803ASTZ datasheet(31/56 Pages) AD

31 / 56 page

ADAV803

Rev. 0 | Page 31 of 56

AD1

AD0

AD1

AD0

SCL

SDA

START BY

MASTER

ED)

SDA

(CONTINUED)

FRAME 1

CHIP ADDRESS BYTE

FRAME 4

FRAME 2

REPEATE

BY MA

ADAV803

ACK. BY

ADAV803

ACK. BY

ADAV803

STOP BY

MASTER

ADAV803

SCL

(CONTINU

FRAME 3

STER

CHIP ADDRESS BYTE

D START

ACK. BY

R/W

Figure 54. Reading from the DAC Left Volume Register in I2C

DS AN

ADAV803 provid

e ability to write to or

ead from a block of re

uous operation. To

e this feature, the us

providing data frames

efore the stop conditi

tion, the register

maticall

ame and the register

egister address.

or a read operation, t

utomatically

cremented with each

ata is

locked out on that fra

Care should be exercised when using the block read or block

write modes. For most cases, block reading or writing to a

to the next register. The exceptions to this case are the indirect

memory address registers, transmitter user bit and receiver user

bit data buffers. Using a block read or write to access these

registers does not update the absolute register address, but

instead updates the buffer address to provide the next value in

the buffer.

BLOCK REA

D WRITES

The

es the user with th

gisters in one contin

er has to continue

on. For a write opera

address is auto

y incremented with each additional

data is written to that r

he register address is a

additional frame, and the register d

me.

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ADAV803ASTZ 数据表(PDF) 31 Page - Analog Devices

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