ADAV803ASTZ datasheet(43/56 Pages) AD

43 / 56 page

ADAV803

Rev. 0 | Page 43 of 56

tatus Buffer

RCS

SB0

Table 47. Receiver Channel S

B7–RC

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS

000 to 01

(0x20 to

= 0100

10111

0x37)

RCSB7–0

The 24-byte receiver channel status buffer. The PRO b

d at ad

tion 0

This bu

only if the channel status is not autob

betwee

ceiver an

mitter.

it is store

dress loca

x20, Bit 0.

ffer is rea

uffered

n the re

d trans

Table 48. T

ter Ch

tus Bu

TCS

ransmit

annel Sta

ffer

B7–TCS

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS

to 10

38 to

= 0111000

01111 (0x

0x4F)

TCSB7–0

The 24-byte transmi

el stat

The PR

tored a

location 0x38, Bit 0. This buffer is

disa

autob

etwee

iver and transmitter is

tter chann

us buffer.

O bit is s

t address

bled when

uffering b

n the rece

enabled.

Table 49. Receiver User Bit Buffer Indire

ess Regi

RxUBADDR07–RxUBADDR00

ct Addr

ster

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 1010000 (0x50)

RxUBADDR07–00

ng to th

ss loca

he rece

r bit bu

Indirect address pointi

e addre

tion in t

iver use

ffer.

Table 50. Receiver Us

07–RxUBDATA00

er Bit Buffer Data Register

RxUBDATA

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 1010001 (0x51)

RxUBDATA07–00

egister reads eight bits of user data from the receiver user bit buffer pointed to by RxUBADDR07–

ering of the user bits is enabled; otherwise, it is a read-only buffer.

A read from this r

00. This buffer can be written to when autobuff

Table 51. Transmitte

Indirect Address Register

BADDR00

r User Bit Buffer

TxUBADDR07–TxU

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 1010010 (0x52)

TxUBADDR07–00

ress pointing to the address location in the transmitter user bit buffer.

Indirect add

Table 52. Transmitter User Bit Buffer

DATA00

Data Register

07–TxUB

TxUBDATA

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 1010011 (0x53)

TxUBDATA07–00

A write to this register writes eight bits of user data to the transmit user bit buffer pointed to by TxUBADDR07–00.

When user bit autobuffering is enabled, this buffer is disabled.

Table 53. Q Subcode CRCError Status Register (Read-Only)

RES

QCRCERROR

QSUB

ADDRESS = 1010100 (0x54)

QCRCERROR

This bit is set, if the CRC check of the Q subcode fails. This bit remains high, but does not generate an interrupt. This

bit is cleared once the register is read.

QSUB

This bit is set, if a Q subcode has been read into the Q subcode buffer (see Table 54).

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