ADAV803ASTZ datasheet(34/56 Pages) AD

34 / 56 page

ADAV803

Rev. 0 | Page 34 of 56

RES

SPMO

MODE0

Table 22. Auxiliary Output Port Register

RES

CLKSR

KSRC0

WLEN

DE1

ADDRESS = 0000111 (0x07)

CLKSRC1–0

CLK.

Selects the clock source for generating the OAUXLRCLK and OAUXB

00 = Auxiliary record port is a slave.

01 = Recovered PLL clock.

ecord port.

10 = Internal Clock 1.

11 = Internal Clock 2.

WLEN1–0

Selects the serial output word length.

00 = 24 bits.

01 = 20 bits.

10 = 18 bits.

11 = 16 bits.

SPMODE1–0

Selects the serial format of the auxiliary r

00 = Left-justified.

01 = I2S.

10 = Reserved.

11 = Right-justified.

Table 23. Group Dela

GRPDLY6–0

y and Mute Register

MUTE_SRC

6, 5, 4, 3, 2, 1, 0

ADDRESS = 0001000 (0x08)

MUTE_SRC

Soft-mutes the output of the sample rate converter.

0 = No mute.

y to the sample rate converter FIR filter by GRPDLY6–0 inpu

ples.

00000 = No de

1 = 1 sample delay.

1 = Soft-mute.

GRPDLY6–0

Adds dela

t sam

lay

000000

0000010 = 2 sample delay.

1111110 = 126 sample delay.

1111111 = 127 sample delay.

ADAV803ASTZ 数据表(PDF) 34 Page - Analog Devices

ADAV803ASTZ 数据表(HTML) 34 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

数据表下载