ADAV803ASTZ datasheet(33/56 Pages) AD

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ADAV803

Rev. 0 | Page 33 of 56

Table 20. Auxiliary Input Port Register

RES

CLKSRC1

CLKSRC0

SPMODE

SPMODE1

SPMODE0

ADDRESS = 0000101 (0x05)

CLKSRC1–0

Selects the clock source for generating the IAUXLRCLK and IAUXBCLK.

00 = Input port is a slave.

01 = Recovered PLL cock.

10 = Internal Clock 1.

11 = Internal Clock 2.

SPMODE2–0

ut port.

tified.

right-justified.

ustified.

Selects the serial format of auxiliary inp

000 = Left-jus

001 = I2S.

100 = 24-bit,

101 = 20-bit,

110 = 18-bit, right-justified.

111 = 16-bit, right-j

Table 21. Record Por

RES

CLKSRC1

CLKSRC0

WLEN1

WLEN0

SPMODE1

SPMODE0

t Control Register

ADDRESS = 0000110 (0x06)

CLKSRC1–0

Selects the clock source for gen

RCLK and OBCLK.

erating the OL

00 = Record port is a slave.

covered PLL clock.

lock 2.

l output word length.

record port.

01 = I2S.

10 = Reserved.

11 = Right-justified.

01 = Re

10 = Internal Clock 1.

11 = Internal C

WLEN1–0

Selects the seria

00 = 24 bits.

01 = 20 bits.

10 = 18 bits.

11 = 16 bits.

SPMODE1–0

Selects the serial format of the

00 = Left-justified.

ADAV803ASTZ 数据表(PDF) 33 Page - Analog Devices

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