ADAV803ASTZ datasheet(26/56 Pages) AD

26 / 56 page

ADAV803

Rev. 0 | Page 26 of 56

er Bit Buffer Size

Table 11. RxBCONF3 Functionality

RxBCONF0

Receiver Us

384 bits with Preamble Z as the start of the block.

768 bits with Preamble Z as the start of the block.

The updating of the user bit buffer is controlled by Bits

RxBCONF2–1 and Bit 7 to Bit 4 of the channel status register, as

shown in Table 12 and Table 13.

Table 12. RxBCONF2–1 Functionality

RxBCONF

Bit 2

Bit 1

Receiver User Bit Buffer Configuration

User bits are ignored.

Update second buffer when first buffer is full.

Format according to Byte 1, Bit 4 to Bit 7, if

PRO bit is set. Format according to

IEC60958-3, if PRO bit is clear.

Table 13. Automatic User Bit Configuration

Bits

Automatic Receiver User Bit Buffer

Configuration

User bits are ignored.

AES-18 format: the user bit buffer is treated in

the same way as when RxBCONF2–1 = 0b01.

User bit buffer is updated in the same way as

when RxBCONF2–1 = 0b01 and RxBCONF0 =

0b00.

User-defined format: the user bit buffer is

treated in the same way as when RxB

= 0b01.

CONF2–1

When the user bit buffer has been filled, the RxUBINT

interrupt bit in the interrupt status register is set, provided that

the RxUBINT mask bit is set, to indicate that the buffer has new

information and can be read.

e first 10 bytes

for one channel of channel status informa-

the TxCSSWITCH bit determines if the data

the

e 48

For the special case when the user data is formatted according

to the IEC60958-3 standard into messages made of information

units, called IUs, the zeros stuffed between each IU and each

message are removed and only the IUs are stored. Once the e

of the message is sensed by more that eight zeros between IU

the user bit buffer is updated with the complete message and t

first buffer begins looking for the start of the next message.

Each IU is stored as a byte consisting of 1, Q, R, S, T, U, V, and W

bits (see the IEC60958-3 specification for more information).

When 96 IUs are received, the Q subcode of the IUs is stored in

the Q subcode buffer, consisting of 10 bytes. The Q subcode is

the Q bits taken from each of the 96 IUs. Th

(80 bits) of the Q subcode contain information sent by CD, MD,

and DAT systems. The last 16 bits of the Q subcode are used to

perform a CRC check of the Q subcode. If an error occurs in

the CRC check of the Q subcode, the QCRCERROR bit is set

This is a sticky bit that remains high until the register is read

Transmitter Operation

The SPDIF transmitter has a similar buffer structure to the

receive section. The transmitter channel status buffer occupies

24 bytes of the register map. This buffer is long enough to store

the 192 bits required

tion. Setting

loaded to the transmitter channel status buffer is intended for

Channel A or Channel B. In most cases, the channel status bits

for Channel A and Channel B are the same, in which case

setting the Tx_A/B_Same bit reads the data from the trans-

mitter channel status buffer and transmits it on both channels.

Because the channel status information is rarely changed during

transmission, the information contained in the buffer is

transmitted repeatedly. The Disable_Tx_Copy bit can be used

prevent the channel status bits from being copied from

transmitter CS buffer into the SPDIF transmitter buffer until

the user has finished loading the buffers. This feature is typically

used, if the Channel A data and Channel B data are different.

Setting the bit prevents the data from being copied. Clearing

bit allows the data to be copied and then transmitted. Figur

shows how the buffers are organize

TxCSSWITCH

TRANSMIT

CS BUFFER

(0x38–0x4F)

CHANNEL

STATUS A

(24 × 8 BITS)

BITS)

CHANNEL

STATUS B

(24 × 8

DITOUT

SPDIF

TRANSMIT

FFER

uffer

As with the receiver section, the transmitted user bits are also

uired, because, unlike the channel

ble. If

ransmitter User Bit Buffer Configurations

TxBCONF2-1

Figure 48. Transmitter Channel Status B

double-buffered. This is req

status bits, the user bits do not necessarily repeat themselves.

The user bits can be buffered in various configurations, as listed

in Table 14. Transmission of the user bits is determined by the

state of the BCONF3 bit. If the bit is 0, the user bits begin

transmitting right away without alignment to the Z pream

this bit is 1, the user bits do not start transmitting until a

Z preamble occurs when the TxBCONF2–1 bits are 01.

Table 14. T

Bit 2

Bit 1

Transmitter User Bit Buffer Configuration

Zeros are transmitted for the user bits.

Host writes user bits to the buffer until it is full.

Writes the user bits to the buffer in IUs

specified by IEC60958-3 and transmits them

according to the standard.

First 10 bytes of the user-bit buffer are

configured to store a Q subcode.

ADAV803ASTZ 数据表(PDF) 26 Page - Analog Devices

ADAV803ASTZ 数据表(HTML) 26 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

数据表下载