MCP48FVB08 datasheet(69/112 Pages) MICROCHIP

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DS20006362A-page 69

MCP48FXBX4/8

TABLE 5-2:

THEORETICAL STEP

VOLTAGE (VS)(1)

5.4.4

OUTPUT SLEW RATE

Figure 5-6 shows an example of the slew rate for the

VOUT pin. The slew rate can be affected by the charac-

teristics of the circuit connected to the VOUT pin.

FIGURE 5-6:

VOUT Pin Slew Rate.

5.4.4.1

Small Capacitive Load

With a small Capacitive Load (CL), the output buffer’s

current is not affected, but the VOUT pin’s voltage is not

a step transition from one output value (DAC register

value) to the next output value. The change of the VOUT

voltage is limited by the output buffer’s characteristics,

so the VOUT pin voltage will have a slope from the old

voltage to the new one. This slope is fixed for the output

buffer and is referred to as the Buffer Slew Rate

(SRBUF).

5.4.4.2

Large Capacitive Load

With a larger capacitive load, the slew rate is determined

by two factors:

• The output buffer’s Short-Circuit Current (ISC)

•The VOUT pin’s external load

IOUT cannot exceed the output buffer’s Short-Circuit

Current (ISC), which fixes the output Buffer Slew Rate

(SRBUF). The voltage on the Capacitive Load, VCL,

changes at a rate proportional to IOUT, which fixes a

Capacitive Load Slew Rate (SRCL).

The VCL voltage slew rate is limited to the slower of the

output buffer’s internally set Slew Rate (SRBUF) and

the Capacitive Load Slew Rate (SRCL).

5.4.5

DRIVING RESISTIVE AND

CAPACITIVE LOADS

The VOUT pin can drive up to 100 pF of capacitive load

in parallel with a 5 k

 resistive load (to meet electrical

specifications).

VOUT drops slowly as the load resistance decreases

after about 3.5 k

. It is recommended to use a load with

RL greater than 5 k.

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase mar-

gin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response with overshoot and ringing in the step

response. That is, since the VOUT pin’s voltage does

not quickly follow the buffer’s input voltage (due to the

large capacitive load), the output buffer will overshoot

the desired target voltage. Once the driver detects this

overshoot, it compensates by forcing it to a voltage

below the target. This causes voltage ringing on the

VOUT pin.

When driving large capacitive loads with the output

buffer, a small Series Resistor (RISO) at the output (see

Figure 5-7) improves the output buffer’s stability (feed-

back loop’s phase margin) by making the output load

resistive at higher frequencies. The bandwidth will be

generally lower than the bandwidth with no capacitive

load.

FIGURE 5-7:

Circuit to Stabilize the

Output Buffer for Large Capacitive Loads (CL).

The RISO resistor value for your circuit needs to be

selected. The resulting frequency response peaking

and step response overshoot for this RISO resistor

value should be verified on the bench. Modify the

RISO’s resistance value until the output characteristics

meet your requirements.

A method to evaluate the system’s performance is to

inject a step voltage on the VREF pin and observe the

VOUT pin’s characteristics.

VREF

5.0

2.7

1.8

1.5

1.0

1.22 mV 659 µV 439 µV 366 µV 244 µV 12-bit

4.88 mV 2.64 mV 1.76 mV 1.46 mV 977 µV 10-bit

19.5 mV 10.5 mV 7.03 mV 5.86 mV 3.91 mV 8-bit

Note 1:

When Gain = 1x, VFS = VRL and VZS = 0V.

Time

DACn = A

VOUT(A)

VOUT(B)

DACn = B

Slew Rate

VOUT B



VOUT A



–

T

--------------------------------------------------

Note:

Additional insight into circuit design for

driving capacitive loads can be found in

AN884, “Driving Capacitive Loads with

Op Amps” (DS00884).

VOUT

RISO

VCL

–

Gain

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