MCP48FVB08 datasheet(87/112 Pages) MICROCHIP

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DS20006362A-page 87

MCP48FXBX4/8

FIGURE 7-13:

8-Bit Enable Command (C1:C0 = 10) – SPI Waveforms (Mode 0,0).

7.10

Disable Configuration Bit

(High Voltage)

Figure 7-14 shows the formats for a single disable

Configuration bit command. The command will only

start an EEPROM Write Cycle (tWC) after a properly

formatted command has been received.

During an EEPROM write cycle, only serial commands

to volatile memory are accepted. All other serial

commands are ignored until the EEPROM Write Cycle

(tWC) completes. This allows the host controller to oper-

ate on the volatile DAC, the volatile VREF, Power-Down,

Gain and Status, and WiperLock Technology Status

registers. The EEWA bit in the Status register indicates

the status of an EEPROM write cycle.

FIGURE 7-14:

Disable Command Sequence.

AD2

AD1

AD4

AD3

AD0

CMDERR

SDI

VIH

VIL

VIH

VIHH

SDO

SCK

HVC

Input

Sample

Note 1:

If an error condition occurs (CMDERR = 0), all the following SDO bits will be low until the CMDERR

condition is cleared (the CS pin is forced to the Inactive state).

The CMDERR bit will be forced to ‘0’, regardless if this Address+Command combination is valid. This

command will not be completed and requires the CS pin to return to VIH to clear the CMDERR

condition.

SDI *

SDO

1 Valid(1)

00 Invalid(2)

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