MCP48FVB08 datasheet(70/112 Pages) MICROCHIP

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MCP48FXBX4/8

DS20006362A-page 70

 2020 Microchip Technology Inc.

5.5

Power-Down Operation

To allow the application to conserve power when the

DAC operation is not required, three Power-Down

modes are available. The Power-Down configuration

bits (PDnB:PDnA) control the power-down operation

(Figure 5-8 and Table 5-3). On devices with multiple

DACs, each DACs Power-Down mode is individually

controllable. All Power-Down modes do the following:

• Turn off most DAC module’s internal circuits

(output op amp, resistor ladder, etc.)

• Op amp output becomes high-impedance to the

VOUT pin

• Disconnect the resistor ladder from the Reference

Voltage (VRL)

• Retain the value of the volatile DAC register and

Configuration bits and the nonvolatile (EEPROM)

DAC register and Configuration bits

Depending on the selected Power-Down mode, the

following will occur:

•VOUT pin is switched to one of the two resistive

pull-downs (see Table 5-4):

- 125 k

 (typical)

-1 k

 (typical)

• Op amp is powered down and the VOUT pin

becomes high-impedance

There is a delay (TPDE) between the PDnB:PDnA bits,

changing from ‘00’ to either ‘01’, ‘10’ or ‘11’, with the op

amp no longer driving the VOUT output and the pull-down

resistors sinking current.

FIGURE 5-8:

VOUT Power-Down Block

Diagram.

In any of the Power-Down modes where the VOUT pin

is not externally connected (sinking or sourcing cur-

rent), the power-down current will typically be 680 nA

for a quad DAC device. As the number of DACs

increases, the device’s power-down current will also

increase.

The Power-Down bits are modified by using a WRITE

command to the volatile Power-Down register or a POR

event which transfers the nonvolatile Power-Down

Table 5-4 shows the current sources for the DAC based

on the selected source of the DAC’s reference voltage

and if the device is in a normal operating mode or in

one of the Power-Down modes.

Section 7.0 “SPI Device Commands” describes the

SPI commands for writing the power-down bits. The com-

mand that can update the volatile PDnB:PDnA bits is a

WRITE command (normal and high voltage).

Gain

(1x or 2x)

VOUT

PDnB:PDnA

VDD

PDnB:PDnA

TABLE 5-3:

POWER-DOWN BITS AND

OUTPUT RESISTIVE LOAD

PDnB PDnA

Function

Normal operation

 resistor to ground

125 k

 resistor to ground

Open circuit

TABLE 5-4:

DAC CURRENT SOURCES

Device VDD

Current

Source

PDnB:A = 00,

VRnB:A =

PDnB:A

 00,

VRnB:A =

00 01 10 11 00 01 10 11

Output Op Amp Y

Resistor

Ladder

YY N(1) YNN N(1) N

RL Op Amp

Band Gap

Note 1:

Current is sourced from the VREF pin, not

the device VDD.

Note:

The SPI serial interface circuit is not

affected by the Power-Down mode. This

circuit remains active in order to receive

any command that might come from the

master device.

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