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MCP48FVB08 数据表(PDF) 77 Page - Microchip Technology

部件名 MCP48FVB08
功能描述  8/10/12-Bit Quad/Octal Voltage Output, 6 LSb INL Digital-to-Analog Converters with SPI Interface
PDF  112 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

MCP48FVB08 数据表(HTML) 77 Page - Microchip Technology

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 2020 Microchip Technology Inc.
DS20006362A-page 77
MCP48FXBX4/8
7.0
SPI DEVICE COMMANDS
The MCP48FXBX4/8 devices’ SPI command format
supports 32 memory address locations and four
commands:
• WRITE command (C1:C0 = 00)
• READ command (C1:C0 = 11)
• Enable Configuration bit (high voltage,
HVC = VIHH):
- Enable Configuration bit (C1:C0 = 10)
- Disable Configuration bit (C1:C0 = 01)
The supported commands are shown in Table 7-1.
These commands allow for both single data or continu-
ous data operation. Table 7-2 also shows the required
number of bit clocks for each command’s different mode
of operation.
Commands may have two modes. These are:
• Normal Serial Commands
• High-Voltage Serial Commands
Normal serial commands are those where the HVC pin
is driven to either VIH or VIL. With high-voltage serial
commands, the HVC pin is driven to VIHH.
The 8-bit commands (see Figure 7-1) are used to mod-
ify the device Configuration bits (Section 7.9 “Enable
Configuration Bit (High Voltage)” and Section 7.10
“Disable Configuration Bit (High Voltage)”) while
the 24-bit commands (see Figure 7-2) are used to read
and write to the device registers (Section 7.8 “READ
Command (Normal and High Voltage)” and
Section 7.7 “WRITE Command (Normal and High
Voltage)”). These commands contain a command byte
and two data bytes.
FIGURE 7-1:
8-Bit SPI Command Format.
7.1
Command Byte
The command byte has three fields: the address, the
command and one reserved bit (see Figure 7-1).
The device memory is accessed when the master
sends a proper command byte to select the desired
operation. The memory location getting accessed is
contained in the command byte’s AD4:AD0 bits. The
action desired is contained in the command byte’s
C1:C0 bits; see Table 7-2. C1:C0 determines if the
desired memory location will be read, written, enabled
or disabled.
As the command byte is being loaded into the device (on
the SDI pin), the device’s SDO pin is driving. The SDO pin
will output high bits for the first seven bits of that com-
mand. On the 8th bit, the SDO pin will output the
CMDERR bit state (see Section 7.6 “Error Condition”).
7.2
Data Bytes
Data bytes are only present in the READ and WRITE
commands. These commands concatenate the two
data bytes, after the command byte, for a 24-bit long
command (see Figure 7-2).
FIGURE 7-2:
24-Bit SPI Command Format.
TABLE 7-1:
COMMAND BITS OVERVIEW
C1:C0 Bit
States
Command
# of Bits Normal or HV
11
Read Data
24 Bits Normal
00
Write Data
24 Bits Normal
01
Enable(1)
8 Bits
HV Only
10
Disable(1)
8 Bits
HV Only
Note 1: High-voltage enable and disable com-
mands on selected nonvolatile memory
locations.
Command Byte
Legend:
AD
4
AD
3
AD
2
AD
1
AD
0
C
1
C
0
X
AD
n
Memory Address
C
n
Command Bits
D
nn
Data Bits
XReserved
Command Byte
Data Word (2 bytes)
Legend:
AD
4
AD
3
AD
2
AD
1
AD
0
C
1
C
0
X
X
X
X
X
D
11
D
10
D
09
D
08
D
07
D
06
D
05
D
04
D
03
D
02
D
01
D
00
AD
n
Memory Address
C
n
Command Bits
D
nn
Data Bits
X Reserved



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