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MCP48FVB08 数据表(PDF) 82 Page - Microchip Technology |
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MCP48FVB08 数据表(HTML) 82 Page - Microchip Technology |
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82 / 112 page ![]() MCP48FXBX4/8 DS20006362A-page 82 2020 Microchip Technology Inc. FIGURE 7-6: Continuous WRITE Commands (Volatile Memory Only). 12-bit data 10-bit data 8-bit data SDI AD 4 AD 3 AD 2 AD 1 AD 0 C 1 C 0 X X X X X D 11 D 10 D 09 D 08 D 07 D 06 D 05 D 04 D 03 D 02 D 01 D 00 ** ** * 0 0 * * * * * * * * * * * * * * * * * SDO XX XX XX X 1 11 11 11 11 11 11 11 11 Valid(2) XX XX XX X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Invalid(3) SDI AD 4 AD 3 AD 2 AD 1 AD 0 C 1 C 0 X X X X X D 11 D 10 D 09 D 08 D 07 D 06 D 05 D 04 D 03 D 02 D 01 D 00 ** ** * 0 0 * * * * * * * * * * * * * * * * * SDO 11 11 11 1 1 11 11 11 11 11 11 11 11 Valid(2) (3) 00 00 00 (4) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Invalid(3) SDI AD 4 AD 3 AD 2 AD 1 AD 0 C 1 C 0 X X X X X D 11 D 10 D 09 D 08 D 07 D 06 D 05 D 04 D 03 D 02 D 01 D 00 ** ** * 0 0 * * * * * * * * * * * * * * * * * SDO 11 11 11 1 1 11 11 11 11 11 11 11 11 Valid(2) (3) 00 00 00 (4) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Invalid(3) (1) (1) (1) Note 1: For WRITE commands addressing the DAC Wiper registers, the data bits depend on the resolution of the device: 12-bit = D11:D00, 10-bit = D09:D00, and 8-bit = D07:D00. Data are right justified for easy host controller operation (no data manipulation before transmitting the desired value). The unimplemented bits are ignored. 2: After a valid memory address and WRITE command byte are received (CMDERR = 1), all the following SDO bits will be output as ‘1’. 3: If an error condition occurs (CMDERR = 0), all the following SDO bits will be output as ‘0’ until the CMDERR condition is cleared (the CS pin is forced to the Inactive state). 4: This CMDERR bit will be forced to ‘0’, regardless if this Address+Command combination is valid. This command will not be completed and requires the CS pin to return to VIH to clear the CMDERR condition. |
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