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MCP48FVB08 数据表(PDF) 16 Page - Microchip Technology |
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MCP48FVB08 数据表(HTML) 16 Page - Microchip Technology |
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16 / 112 page ![]() MCP48FXBX4/8 DS20006362A-page 16 2020 Microchip Technology Inc. DC Notes: 1. This parameter is ensured by design. 2. This parameter is ensured by characterization. 3. POR/BOR voltage trip point is not slope-dependent. Hysteresis is implemented with time delay. 4. Supply current is independent of current through the resistor ladder in mode VRnB:VRnA = 10. 5. The PDnB:PDnA bits = 01, 10 and 11 configurations should have the same current. 6. Resistance is defined as the resistance between the VREF pin (mode VRnB:VRnA = 10) to VSS pin. For octal-channel devices (MCP48FXBX8), this is the effective resistance of each resistor ladder. The resistance measurement is one of the two resistor ladders measured in parallel. 7. INL and DNL are measured at VOUT with VRL = VDD (VRnB:VRnA = 00). 8. This gain error does not include an offset error. 9. Within 1/2 LSb of the final value when the code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in a 12-bit device.) 10. Code range is dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit, codes 100 to 4000. 11. Variation of one output voltage to mean output voltage. |
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