MCP48FVB08 datasheet(76/112 Pages) MICROCHIP

76 / 112 page

MCP48FXBX4/8

DS20006362A-page 76

 2020 Microchip Technology Inc.

6.3.1

SERIAL DATA IN (SDI)

The Serial Data In (SDI) signal is the data signal into

the device. The value on this pin is latched on the

rising edge of the SCK signal.

6.3.2

SERIAL DATA OUT (SDO)

The Serial Data Out (SDO) signal is the data signal out

of the device. The value on this pin is driven on the

falling edge of the SCK signal.

Once the CS pin is forced to the active level (VIL or

VIHH), the SDO pin will be driven. The state of the

SDO pin is determined by the serial bit’s position in the

command, the command selected and if there is a

Command Error (CMDERR) state.

6.3.3

SERIAL CLOCK (SCK)

(SPI FREQUENCY OF OPERATION)

The SPI interface is specified to operate up to 20 MHz.

The actual clock rate depends on the configuration of

the system and the serial command used. Table 6-1

shows the SCK frequency for different configurations.

6.3.4

CS SIGNAL

The Chip Select (CS) signal is used to select the

device and frame a command sequence. To start a

command, or sequence of commands, the CS signal

must transition from the Inactive state (VIH) to an

Active state (VIL or VIHH).

After the CS signal has gone active, the SDO pin is

driven and the clock bit counter is reset.

If an error condition occurs for an SPI command, then

the command byte’s Command Error (CMDERR) bit

(on the SDO pin) will be driven low (VIL). To exit the

error condition, the user must take the CS pin to the

VIH level.

When the CS pin returns to the Inactive state (VIH), the

SPI module resets (including the Address Pointer).

While the CS pin is in the Inactive state (VIH), the serial

interface is ignored. This allows the host controller to

interface to other SPI devices using the same SDI,

SDO and SCK signals.

6.3.5

HVC SIGNAL

The high-voltage capability of the HVC pin allows High-

Voltage Commands. High-Voltage Commands allow the

device’s WiperLock technology and write-protect

features to be enabled and disabled.

6.4

Communication Data Rates

The MCP48FXBX4/8 devices support clock rates (bit

rate) of up to 20 MHz for WRITE commands and

10 MHz for READ commands.

For most applications, the write time will be considered

more important, since that is how the device operation

is controlled.

6.5

POR/BOR

On a POR/BOR event, the SPI serial interface module

state machine is reset, which means that the device’s

Memory Address Pointer is forced to 00h.

TABLE 6-1:

SCK FREQUENCY

Memory Type Access

Command

Read

Write,

Enable,

Disable

Nonvolatile

Memory

SDI, SDO

10 MHz

20 MHz(1,2)

Volatile

Memory

SDI, SDO

10 MHz

20 MHz(2)

Note 1:

After a WRITE command, the internal

write cycle must be completed before the

next SPI command is received.

This is a design goal. The SDO pin

performance is believed to be the limiting

factor.

Note: There is a required delay after the CS pin

goes active to the first edge of the SCK pin.

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