MCP48FVB08 datasheet(80/112 Pages) MICROCHIP

80 / 112 page

MCP48FXBX4/8

DS20006362A-page 80

 2020 Microchip Technology Inc.

7.7.2

SINGLE WRITE TO NONVOLATILE

MEMORY

The sequence to write to a single nonvolatile memory

location is the same as a single write to volatile memory,

with the exception that after the CS pin is driven inactive

(VIH), the EEPROM Write Cycle (tWC) is started. A write

cycle will not start if the WRITE command is not exactly

24 clock pulses. This protects against system issues

corrupting the nonvolatile memory locations.

Once a WRITE command to a nonvolatile memory

location has been received, no other SPI commands

should be received before the CS pin transitions to the

Inactive state (VIH) or the current SPI command will

have a Command Error (CMDERR) occur.

After the CS pin is driven inactive (VIH), the serial

interface may immediately be re-enabled by driving

the CS pin to the Active state (VIL).

During an EEPROM write cycle, access to the volatile

memory is allowed when using the appropriate com-

mand sequence. Commands that address nonvolatile

memory are ignored until the EEPROM Write Cycle

(tWC) completes. This allows the host controller to

operate on the volatile DAC registers.

7.7.3

CONTINUOUS WRITES TO

VOLATILE MEMORY

A Continuous Write mode of operation is possible when

writing to the device’s volatile memory registers (see

Table 7-3). Figure 7-6 shows the sequence for three

continuous writes. The writes do not need to be to the

same volatile memory address.

7.7.4

CONTINUOUS WRITES TO

NONVOLATILE MEMORY

Continuous writes to nonvolatile memory are not

allowed and attempts to do so will result in a

Command Error (CMDERR) condition.

7.7.5

HIGH-VOLTAGE COMMAND (HVC)

SIGNAL

The High-Voltage Command (HVC) signal is used to

indicate that the command or sequence of commands

are in the high-voltage operational state. HVC

commands allow the device’s WiperLock technology

and write-protect features to be enabled and disabled.

FIGURE 7-3:

Write Single Memory Location Command – SDI and SDO States.(1)

Note:

The EEWA status bit indicates if an

EEPROM write cycle is active (see

TABLE 7-3:

VOLATILE MEMORY

ADDRESSES

Address

Quad-Channel

Octal-Channel

00h-03h

Yes

04h-07h

Yes

08h

Yes

09h

Yes

0Ah

Yes

Note:

Writes to a volatile DAC register will not

transfer to the output register until the LAT

(HVC) pin is transitioned from the VIHHEN

voltage to a VIL voltage.

Note 1:

For WRITE commands addressing the DAC Wiper registers, the data bits depend on the resolution of the

device: 12-bit = D11:D00, 10-bit = D09:D00 and 8-bit = D07:D00. Data are right justified for easy host

controller operation (no data manipulation before transmitting the desired value). The unimplemented bits

are ignored.

2: After a valid memory address and WRITE command byte are received (CMDERR = 1), all the following

SDO bits will be output as ‘1’.

3: If an error condition occurs (CMDERR = 0), all the following SDO bits will be output as ‘0’ until the

CMDERR condition is cleared (the CS pin is forced to the Inactive state).

12-bit data

10-bit data

8-bit data

SDI

SDO

11 Valid(2)

0 Invalid(3)

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