MCP48FVB08 datasheet(71/112 Pages) MICROCHIP

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DS20006362A-page 71

MCP48FXBX4/8

5.5.1

EXITING POWER-DOWN

When the device exits Power-Down mode, the

following occurs:

• Disabled circuits (op amp, resistor ladder, etc.)

are turned on

• The resistor ladder is connected to the selected

Reference Voltage (VRL)

• The selected pull-down resistor is disconnected

•The VOUT output will be driven to the voltage

represented by the volatile DAC register’s value

and Configuration bits

The VOUT output signal requires time as these circuits

are powered up and the output voltage is driven to the

specified value as determined by the volatile DAC

Any WRITE command where the PDnB:PDnA bits are

‘00’ will cause the device to exit the Power-Down mode.

5.6

DAC Registers, Configuration Bits

and Status Bits

The MCP48FXBX4/8 device family has both volatile

and nonvolatile (EEPROM) memory options. Table 4-2

shows the volatile and nonvolatile memory, and their

interaction due to a POR event.

There are five Configuration bits, DAC registers, and two

volatile status bits in both the volatile and nonvolatile

memory. The DAC registers (volatile and nonvolatile) will

be either twelve bits (MCP48FXB2X), ten bits

(MCP48FEB1X) or eight bits (MCP48FXB0X) wide.

When the device is first powered up, it automatically

uploads the EEPROM memory values or factory

default values (in case of MCP48FVBXX devices) to

the volatile memory. The volatile memory determines

the analog Output Voltage (VOUT) pin. After the device

is powered up, the user can update the memory.

This memory is read and written through the SPI inter-

face. See Section 6.0 “SPI Serial Interface Module”

and Section 7.0 “SPI Device Commands” for more

details on reading and writing the device’s memory.

When the nonvolatile memory is written, the device

starts writing the EEPROM cell at the Acknowledge

pulse of the WRITE single memory location command.

bits and Table 4-2 shows the factory default value of a

POR/BOR event for the device Configuration bits.

There are two status bits. These are only in volatile

memory and indicate the status of the device. The POR

bit indicates if the device VDD is above or below the

POR trip point. During normal operation, this bit should

be ‘1’. The EEWA bit indicates if an EEPROM write

cycle is in progress. While the EEWA bit is ‘1’ (during

the EEPROM writing), all commands are ignored,

except for the READ command.

Note:

Since the op amp and resistor ladder are

powered off (0V), the op amp’s Input

Voltage (VW) can be considered 0V. There

delay

(TPDD) between the

PDnB:PDnA bits updating to ‘00’ and the

op amp driving the VOUT output. The

op amp’s settling time (from 0V) needs to

be taken into account to ensure the VOUT

voltage reflects the selected value.

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