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MCP48FVB08 数据表(PDF) 84 Page - Microchip Technology

部件名 MCP48FVB08
功能描述  8/10/12-Bit Quad/Octal Voltage Output, 6 LSb INL Digital-to-Analog Converters with SPI Interface
PDF  112 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

MCP48FVB08 数据表(HTML) 84 Page - Microchip Technology

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MCP48FXBX4/8
DS20006362A-page 84
 2020 Microchip Technology Inc.
7.8.3
CONTINUOUS READS
Continuous reads format allows the device’s memory
to be read quickly. Continuous reads are possible to all
memory locations. If a nonvolatile memory write cycle
is occurring, then READ commands may only access
the volatile memory locations.
Figure 7-8 shows the sequence for three continuous
reads. The reads do not need to be to the same
memory address.
This is useful in reading the System Status register
(0Ah) to determine if an EEPROM write cycle is
complete (EEWA bit).
FIGURE 7-8:
READ Command – Continuous Read Sequence.
12-bit data
10-bit data
8-bit data
SDI
AD
4
AD
3
AD
2
AD
1
AD
0
C
1
C
0
X
X
X
X
X
D
11
D
10
D
09
D
08
D
07
D
06
D
05
D
04
D
03
D
02
D
01
D
00
**
**
*
0
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
SDO
XX
XX
XX
X
1
00
00
11
11
11
11
11
11 Valid(1)
XX
XX
XX
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Invalid(2)
SDI
AD
4
AD
3
AD
2
AD
1
AD
0
C
1
C
0
X
X
X
X
X
D
11
D
10
D
09
D
08
D
07
D
06
D
05
D
04
D
03
D
02
D
01
D
00
**
**
*
0
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
SDO
11
11
11
1
1
00
00
11
11
11
11
11
11 Valid(1)
00
00
00
0 (3) 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Invalid(2)
SDI
AD
4
AD
3
AD
2
AD
1
AD
0
C
1
C
0
X
X
X
X
X
D
11
D
10
D
09
D
08
D
07
D
06
D
05
D
04
D
03
D
02
D
01
D
00
**
**
*
0
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
SDO
11
11
11
1
1
00
00
11
11
11
11
11
11 Valid(1)
00
00
00
0 (3) 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Invalid(2)
Note 1:
The data bits depend on the resolution of the device: 12-bit = D11:D00, 10-bit = D09:D00, and
8-bit = D07:D00. The unimplemented bits are output as ‘0’ and data are right justified for easy host
controller operation (no data manipulation after reading the register value).
2:
If an error condition occurs (CMDERR = 0), all the following SDO bits will be output as ‘0’ until the
CMDERR condition is cleared (the CS pin is forced to the Inactive state).
3:
The CMDERR bit will be forced to ‘0’, regardless if this Address+Command combination is valid. This
command will not be completed and requires the CS pin to return to VIH to clear the CMDERR
condition.



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