MCP48FVB08 datasheet(72/112 Pages) MICROCHIP

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MCP48FXBX4/8

DS20006362A-page 72

 2020 Microchip Technology Inc.

5.7

Latch Pins (LATn)

The Latch pins control when the volatile DAC register

value is transferred to the DAC wiper. This is useful for

applications that need to synchronize the wiper(s)

updates to an external event, such as zero-crossing or

updates to the other wipers on the device. The LAT pin

functionality is asynchronous to the serial interface

operation.

When the LAT pin is high, transfers from the volatile DAC

When the LAT pin is low, the volatile DAC register value

is transferred to the DAC wiper.

Figure 5-9 shows the interaction of the LAT pin and the

loading of the DAC Wiper n (from the volatile DAC

is held low, the corresponding DAC wiper is updated as

soon as the volatile DAC register value is updated.

The LAT pin allows the DAC wiper to be updated to

external

event

and

have

multiple

DAC

channels/devices updating at a common event.

FIGURE 5-9:

LAT and DAC Interaction.

Since the DAC wiper n is updated from the volatile DAC

LAT pin can be updated synchronously.

If the application does not require synchronization, then

this signal should be tied low.

Figure 5-10 shows two examples of using the LAT pin

to control when the Wiper register is updated relative to

the value of a sine wave signal.

FIGURE 5-10:

LAT Pin Operation Example.

Note:

This allows the volatile DAC0 through

DAC7 registers to be updated while the

LATn pins are high, and to have outputs

synchronously updated as the LATn pins

are driven low.

WRITE Command

Vol. DAC Register n

DAC Wiper n

16 Clocks

LAT

SYNC

Transfer

Serial Shift Reg.

Data

(internal signal)

LAT SYNC

Transfer

Data

Comment

No Transfer

Vol. DAC Register n

 DAC Wiper n

No Transfer

Case 1: Zero-Crossing of Sine Wave to Update the Volatile DAC0 Register (using LAT pin)

Case 2: Fixed-Point Crossing of Sine Wave to Update the Volatile DAC0 Register (using LAT pin)

Indicates Where LAT Pin Pulses are Active (volatile DAC0 register updated)

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