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MCP48FVB08 数据表(PDF) 104 Page - Microchip Technology |
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MCP48FVB08 数据表(HTML) 104 Page - Microchip Technology |
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104 / 112 page  MCP48FXBX4/8 DS20006362A-page 104 2020 Microchip Technology Inc. B.4 Full-Scale Error (EFS) The Full-Scale Error (see Figure B-3) is the error on the VOUT pin relative to the expected VOUT voltage (theoretical) for the maximum device DAC register code (code FFFh for 12-bit, code 3FFh for 10-bit and code FFh for 8-bit); see Equation B-2. The error depends on the resistive load on the VOUT pin (and where that load is tied to, such as VSS or VDD). For loads (to VSS) greater than specified, the Full-Scale Error will be greater. The error in bits is determined by the theoretical volt- age step-size to give an error in LSb. EQUATION B-2: FULL-SCALE ERROR B.5 Zero-Scale Error (EZS) The Zero-Scale Error (see Figure B-2) is the difference between the ideal and the measured VOUT voltage with the DAC register code equal to 000h (Equation B-3). The error depends on the resistive load on the VOUT pin (and where that load is tied to, such as VSS or VDD). For loads (to VDD) greater than specified, the Zero-Scale Error will be greater. The error in bits is determined by the theoretical voltage step-size to give an error in LSb. EQUATION B-3: ZERO-SCALE ERROR B.6 Total Unadjusted Error (ET) The Total Unadjusted Error (ET) is the difference between the ideal and the measured VOUT voltage. Typically, calibration of the output voltage is implemented to improve system performance. The error in bits is determined by the theoretical voltage step-size to give an error in LSb. Equation B-4 shows the Total Unadjusted Error calculation. EQUATION B-4: TOTAL UNADJUSTED ERROR CALCULATION Where: EFS is expressed in LSb. VOUT(@FS) = The VOUT voltage when the DAC register code is at full scale. VIDEAL(@FS) = The ideal output voltage when the DAC register code is at full scale. VLSb(IDEAL) = The theoretical voltage step size. EFS VOUT(@FS) VIDEAL(@FS) – VLSb(IDEAL) --------------------------------------------------------------------------- = Where: EZS is expressed in LSb. VOUT(@ZS) =The VOUT voltage when the DAC register code is at zero scale. VLSb(IDEAL) = The theoretical voltage step-size. EZS VOUT(@ZS) VLSb(IDEAL) ---------------------------------- = Where: ET is expressed in LSb. VOUT_Actual(@Code) = The measured DAC output voltage at the specified code. VOUT_Ideal(@Code) = The calculated DAC output voltage at the specified code. (code × VLSb(Ideal)). VLSb(Ideal) =VREF/# Steps 12-bit = VREF/4096 10-bit = VREF/1024 8-bit = VREF/256 ET VOUT_Actual(@Code) VOUT_Ideal(@Code) – VLSb(Ideal) ------------------------------------------------------------------------------------------------------------------------- = |
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