SH7041A datasheet(34/923 Pages) RENESAS

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18.3.1 Port A I/O Register H (PAIORH)......................................................................... 608

18.3.2 Port A I/O Register L (PAIORL) ......................................................................... 609

18.3.3 Port A Control Register H (PACRH) ................................................................... 609

18.3.4 Port A Control Registers L1, L2 (PACRL1 and PACRL2) ................................. 612

18.3.5 Port B I/O Register (PBIOR)................................................................................ 617

18.3.6 Port B Control Registers (PBCR1 and PBCR2)................................................... 618

18.3.7 Port C I/O Register (PCIOR)................................................................................ 622

18.3.8 Port C Control Register (PCCR)........................................................................... 623

18.3.9 Port D I/O Register H (PDIORH)......................................................................... 626

18.3.10 Port D I/O Register L (PDIORL) ......................................................................... 627

18.3.11 Port D Control Registers H1, H2 (PDCRH1 and PDCRH2)................................ 627

18.3.12 Port D Control Register L (PDCRL) .................................................................... 634

18.3.13 Port E I/O Register (PEIOR) ................................................................................ 638

18.3.14 Port E Control Registers 1, 2 (PECR1 and PECR2)............................................. 638

18.3.15 IRQOUT Function Control Register (IFCR)........................................................ 643

18.4

Cautions on Use................................................................................................................. 645

Section 19 I/O Ports (I/O) .................................................................................................. 647

19.1

Overview............................................................................................................................ 647

19.2

Port A................................................................................................................................. 647

19.2.1 Register Configuration ......................................................................................... 650

19.2.2 Port A Data Register H (PADRH)........................................................................ 650

19.2.3 Port A Data Register L (PADRL)......................................................................... 651

19.3

Port B ................................................................................................................................. 652

19.3.1 Register Configuration ......................................................................................... 652

19.3.2 Port B Data Register (PBDR)............................................................................... 653

19.4

Port C ................................................................................................................................. 654

19.4.1 Register Configuration ......................................................................................... 654

19.4.2 Port C Data Register (PCDR)............................................................................... 655

19.5

Port D................................................................................................................................. 656

19.5.1 Register Configuration ......................................................................................... 658

19.5.2 Port D Data Register H (PDDRH)........................................................................ 659

19.5.3 Port D Data Register L (PDDRL)......................................................................... 660

19.6

Port E ................................................................................................................................. 661

19.6.1 Register Configuration ......................................................................................... 661

19.6.2 Port E Data Register (PEDR) ............................................................................... 662

19.7

Port F ................................................................................................................................. 663

19.7.1 Register Configuration ......................................................................................... 663

19.7.2 Port F Data Register (PFDR)................................................................................ 663

Section 20 64/128/256kB Mask ROM........................................................................... 665

20.1

Overview............................................................................................................................ 665

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