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SH7041A 数据表(PDF) 95 Page - Renesas Technology Corp

部件名 SH7041A
功能描述  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

SH7041A 数据表(HTML) 95 Page - Renesas Technology Corp

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57
Table 2.9
Instruction Formats (cont)
Instruction Formats
Source Operand
Destination
Operand
Example
nm format
mmmm: Direct
register
nnnn: Direct
register
ADD
Rm,Rn
nnnn
xxxx
xxxx
15
0
mmmm
mmmm: Direct
register
nnnn: Indirect
register
MOV.L
Rm,@Rn
mmmm: Indirect
post-increment
register (multiply/
accumulate)
nnnn*: Indirect
post-increment
register (multiply/
accumulate)
MACH, MACL
MAC.W
@Rm+,@Rn+
mmmm: Indirect
post-increment
register
nnnn: Direct
register
MOV.L
@Rm+,Rn
mmmm: Direct
register
nnnn: Indirect pre-
decrement
register
MOV.L
Rm,@-Rn
mmmm: Direct
register
nnnn: Indirect
indexed register
MOV.L
Rm,@(R0,Rn)
md format
xxxx
dddd
15
0
mmmm
xxxx
mmmmdddd:
indirect register
with
displacement
R0 (Direct
register)
MOV.B
@(disp,Rm),R0
nd4 format
xxxx
xxxx
dddd
15
0
nnnn
R0 (Direct
register)
nnnndddd:
Indirect register
with displacement
MOV.B
R0,@(disp,Rn)
nmd format
nnnn
xxxx
dddd
15
0
mmmm
mmmm: Direct
register
nnnndddd: Indirect
register with
displacement
MOV.L
Rm,@(disp,Rn)
mmmmdddd:
Indirect register
with
displacement
nnnn: Direct
register
MOV.L
@(disp,Rm),Rn
Note: * In multiply/accumulate instructions, nnnn is the source register.



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